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Understanding Delta-Sigma Data Converters

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
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Proceedings ArticleDOI
15 Jun 2006
TL;DR: In this paper, a digital-to-phase converter operating from 0.5-1.5GHz employs oversampling, noise shaping and DLL phase filtering to achieve sub-ps resolution independent of the operating frequency.
Abstract: A digital-to-phase converter operating from 0.5-1.5GHz employs oversampling, noise shaping and DLL phase filtering to achieve sub-ps resolution independent of the operating frequency. Test chip fabricated in a 0.13mum CMOS process achieves a DNL below plusmn100fs and plusmn12ps INL and consumes 15mW while operating at 1GHz

13 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...The phase quantization error of the DPC can be designed to be lower than the phase noise floor determined by intrinsic noise sources such as thermal and flicker noise....

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Proceedings ArticleDOI
26 Oct 2015
TL;DR: This paper addresses timing synchronization using low frequency real-time clocks in all nodes using a beacon-driven TDMA-protocol for bidirectional node/base communication and proposes to use a ΔΣ-converter to generate a sequence of superframes with different time durations, but each consisting of integer multiples of clock ticks, which achieve the accurate superframe duration for any rational number ofclock ticks.
Abstract: In this paper a novel synchronization method for wireless sensor networks with star topology is presented. We address timing synchronization using low frequency real-time clocks in all nodes. A beacon-driven TDMA-protocol for bidirectional node/base communication is used. Between the beacons, which are sent by the base station, lie the superframe time intervals to handle data transmission from node to base. We discuss the protocol and its energy saving advantages including the challenges of synchronization. We reduce the required communication for synchronization based on long term synchronicity of the node to save energy. Due to the individual node clock, the accurate superframe time interval usually will consist of a rational number of clock ticks. We propose to use a ΔΣ-converter to generate a sequence of superframes with different time durations, but each consisting of integer multiples of clock ticks, which - on average - achieve the accurate superframe duration for any rational number of clock ticks. We show by theory and measurements that our novel approach leads to a variance of the synchronization error which is constant at a value of 0.25 clock cycles. The variance is independent of the rate at which the nodes listen to the beacon of the base station.

13 citations


Cites methods from "Understanding Delta-Sigma Data Conv..."

  • ...The noise transfer function (NTF) of the ∆Σ-converter is given by [13] NTF(z) = 1− z−1 (1)...

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  • ...Computing the PSD of Y and using the linearized transfer function of the averaging filter for the slowly varying input signal T̂SF(e) according to [13] we find |Y (e)|(2) = N(2)|T̂SF(e)|(2)....

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Journal ArticleDOI
TL;DR: The paper presents optimization of the modulator in the design space defined by the filter capacitor ratios and the feedback coefficients and shows that for this purpose the quantization and thermal noise should be considered jointly.
Abstract: In this paper we study passive switched-capacitor sigma-delta ( $\Sigma\Delta $ ) modulators suitable for low power applications. Using a one-bit quantizer as the only active block those modulators save power and achieve high linearity. However, their order is largely limited since the passive loop filter presents a significant attenuation to the signal. Typically with a second-order filter the modulator can achieve a satisfactory signal-to- quantization-noise ratio (SQNR) by using a large enough oversampling ratio (OSR) that also creates a tradeoff with the power consumption. A passive $\Sigma\Delta $ modulator when modeled as a linear system requires extraction of the equivalent loop gain. It is shown that for this purpose the quantization and thermal noise should be considered jointly. The paper presents optimization of the modulator in the design space defined by the filter capacitor ratios and the feedback coefficients. Both circuit and system level behavioral models are extensively exploited for this purpose. Provided is a detailed analysis of the thermal noise, quantization noise, and other parasitic effects. The design verified by 65 nm CMOS chip demonstrates very good agreement with the developed models. The measurements show signal-to-noise-and-distortion ratio (SNDR) of 73 dB and ${\hbox {power ~consumption}} with energy efficiency of 0.27 pJ/step at 0.9 V supply. For supply voltage reduced to 0.7 V the power consumption is 0.47 $\mu {\rm W}$ with ${\rm SNDR}= 71~{\rm dB}$ while energy efficiency is 0.16 pJ/step.

13 citations


Cites background or methods from "Understanding Delta-Sigma Data Conv..."

  • ...modulators for which a higher out-of-band gain would result in lower MSA and vice versa [3]....

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  • ...For second order modulators the upper bound used in this criterion was shown to be replaced by 4 [3]....

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  • ...In this design we make use of the popular cascade-of-integrators with distributed feedback (CIFB) architecture [3] shown in Fig....

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  • ...By oversampling and shaping of the quantization noise, offered by this technique, a high resolution A/D conversion has been enabled [2], [3]....

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Journal ArticleDOI
TL;DR: Modulations of single-loop and double-loop hexagonal sigma-delta modulations for voltage source converters that use silicon carbide (SiC) semiconductors greatly improve efficiency and generate fewer low-order harmonics than the SVPWM and VSFPWM strategies do.
Abstract: The efficiency of wide-bandgap (WBG) power converters can be greatly improved using high-frequency modulation techniques. This article proposes using single-loop and double-loop hexagonal sigma-delta (H- $\Sigma \Delta$ and DH- $\Sigma \Delta$ , respectively) modulations for voltage source converters (VSC) that use silicon carbide (SiC) semiconductors. These allow high switching frequencies to operate more efficiently than silicon devices. Thus, $\Sigma \Delta$ modulations are excellent candidates for taking advantage of WBG devices. The proposed modulation techniques allow working with a variable switching frequency, thus producing an extreme reduction in switching losses and mitigating the low-order harmonics in comparison with the classical space vector pulsewidth modulation (SVPWM) technique, and with the innovative variable switching frequency pulse-width modulation (VSFPWM). The performance and losses of both $\Sigma \Delta$ techniques are analyzed here using MATLAB/Simulink and PLECS, and then compared with SVPWM and VSFPWM. Furthermore, the frequency spectrum and the total harmonic distortion are evaluated. Experimental results performed on a VSC converter that uses SiC MOSFET s show how H- $\Sigma \Delta$ and DH- $\Sigma \Delta$ greatly improve efficiency and generate fewer low-order harmonics than the SVPWM and VSFPWM strategies do.

13 citations

Journal ArticleDOI
TL;DR: Two methods are presented for implementing a multi-channel ADC using a continuous-time delta-sigma modulator (CTDSM) without resetting its states and an adaptive equalizer used for flattening the equivalent frequency response and eliminate memory.
Abstract: Two methods are presented for implementing a multi-channel ADC using a continuous-time delta-sigma modulator (CTDSM) without resetting its states. The first is adapted from a method used with a discrete-time delta-sigma modulator. It uses a sample-and-hold (S/H) at the Nyquist rate before the modulator and an adaptive equalizer at the Nyquist rate after the modulator for flattening the equivalent frequency response and eliminate memory. The newly proposed $\pi $ -shifted filter, instead of flattening the equivalent discrete-time frequency response, merely ensures that the equivalent frequency response is symmetric about $\omega =\pi /2$ . In the time domain, this means that the equivalent impulse response at the Nyquist rate has zero-valued odd samples ensuring no cross-talk between two multiplexed inputs. Compared to the adaptive equalizer used for flattening the frequency response, this filter consumes three times lower power while occupying half the area. A two-channel ADC is demonstrated using both the adaptive equalizer & the $\pi $ -shifted filter. The ADC uses a CTDSM running at 6.144 MHz with an oversampling ratio (OSR) of 64, yielding a per-channel bandwidth of 24 kHz. The prototype in 180nm achieves a peak SNR/SNDR/DR of 91.7 dB/84.9 dB/98 dB and consumes 1.33mW per channel with adaptive equalizer. The SNR/SNDR/DR is 90.5 dB/83.7 dB/97 dB with a power consumption of 0.86mW per channel with the $\pi $ -shifted filter.

13 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...and that the proposed system does not exploit the inherent anti-aliasing property of an NRZ-DAC based CTDSM [10]....

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References
More filters
Journal ArticleDOI
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal ArticleDOI
James C. Candy1
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal ArticleDOI
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book ChapterDOI
James C. Candy1, O. Benjamin1
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal ArticleDOI
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations