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Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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TL;DR: This brief proposes a multiplexing scheme to realize an I/Q-channel time-interleaved (TI) bandpass sigma-delta modulator that shares operational transconductance amplifiers to minimize power consumption and silicon area for a low-intermediate-frequency (IF) wireless receiver.
Abstract: This brief proposes a multiplexing scheme to realize an I/Q-channel time-interleaved (TI) bandpass sigma-delta modulator that shares operational transconductance amplifiers to minimize power consumption and silicon area for a low-intermediate-frequency (IF) wireless receiver. The test chip was fabricated for a 10.7-MHz IF system with a 0.35-mum CMOS process. The measured peak signal-to-noise distortion ratio for a 200-kHz bandwidth is approximately 73 dB. The power consumption of the fabricated chip is 61 mW with a 3.3-V supply, and the silicon area is 1.78 mm2. The measured channel crosstalk is about -48 dB
13 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...It provides the figure-of-merit (FOM) that is defined as follows [12]:...
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TL;DR: The virtual-ground-switched resistor DAC is introduced as a way to achieve low distortion by addressing parasitic resistance in the reference path and reducing the effects of ISI.
Abstract: We present design considerations for CT $\!\Delta \!\Sigma $ Ms that attempt to achieve high resolution (16+ bits) over a wide bandwidth (>200 kHz), resulting in a low in-band noise spectral density. The main challenges in such designs are parasitic resistance in the reference path, inter-symbol interference (ISI) in the feedback-digital-to-analog converter (DAC) waveform, and flicker noise of the input operational transconductance amplifier (OTA). We introduce the virtual-ground-switched resistor DAC as a way to achieve low distortion by addressing parasitic resistance in the reference path and reducing the effects of ISI. Flicker noise is reduced by chopping the first stage of the input OTA. Chopping artifacts and clock jitter sensitivity are reduced by using a three-stage OTA and finite impulse response (FIR) feedback. These techniques are applied to the design of a 250 kHz bandwidth CT $\!\Delta \!\Sigma \text{M}$ targeting 108 dB signal-to-noise-and-distortion-ratio (SNDR) in a 180 nm CMOS process. The fabricated prototype, which operates at 32 MS/s, achieves 105.3/108.1 dB SNDR/signal-to-noise-ratio (SNR) and consumes 24 mW. The Schreier SNDR figure of merit (FoM) is 175.5 dB.
13 citations
Cites background or methods from "Understanding Delta-Sigma Data Conv..."
...For instance, analysis based on [12] shows that a 30 ps difference between the rise and fall times of the single-ended DAC pulse results in HD2 of about 60 dB (for our sampling rate of 32 MHz) in the single-ended current waveforms....
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...A resistor-based design is the most suitable choice to realize the DAC due to its low noise [12]....
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20 Mar 2013TL;DR: In this article, the authors proposed a radio architecture for the wireless monitoring and control of infrastructure equipment, which is useful for machine-to-machine communication using non line-of-sight waves that are multiply reflected by electromagnetic scatters.
Abstract: A radio architecture is proposed for the wireless monitoring and control of infrastructure equipment. The proposed architecture is useful for machine-to-machine communication using non line-of-sight waves that are multiply reflected by electromagnetic scatters, i.e., with equipments that is much larger than the radio. The proposed radio transmits the signal, which is expanded by orthogonal codes, on different wireless paths using different polarization directions at different times. This communication approach results in good resistance against outer interferences and unexpected interruption, which enables it to achieve highly-reliable wireless communication. We designed a prototype radio in 400MHz band. Simulation results indicate that 100kHz data could be successfully reconstructed through 46MHz coding/decoding and 93MHz modulation/demodulation. The 5x up-conversion is enabled by the band-pass delta-sigma circuit that contains digital parts in a commercial field programmable gate array. The prototype radio exhibited a carrier to noise ratio of more than 30dB.
13 citations
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TL;DR: In this paper, a single-loop delta-sigma modulator with extended dynamic range is proposed, which employs an auxiliary quantiser to process the quantisation error of the main quantiser.
Abstract: A single-loop delta-sigma modulator with extended dynamic range is proposed. It employs an auxiliary quantiser to process the quantisation error of the main quantiser. This simple addition guarantees improved stability over a wider signal input range and also reduces the sensitivity to the front-end DAC nonlinearity. Simulation results are provided to verify the effectiveness of this structure.
13 citations
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TL;DR: An oversampling stochastic analog-to-digital converter that spatially averages quantization errors in multiple voltage-controlled oscillator (VCO)-based quantizers and validates the extra 9 dB signal to quantization noise ratio improvement from quantization error spatial averaging.
Abstract: An oversampling stochastic analog-to-digital converter is presented. This stochastic converter spatially averages quantization errors in multiple voltage-controlled oscillator (VCO)-based quantizers. Unlike other stochastic converters, this proposed architecture does not require an inverse Gaussian cumulative density function estimator. The digital adder becomes an ideal estimator due to uncorrelated quantization errors, which can be modeled as a uniformly distributed random variable. Because of the simple open-loop structure, this stochastic converter can easily be synthesized and reconfigured. The proof-of-concept prototype is implemented in a 0.18 $\mu \text{m}$ CMOS process. The prototype employs eight VCO-based quantizers and validates the extra 9 dB signal to quantization noise ratio improvement from quantization error spatial averaging. The measurements further demonstrate 54.2 dB and 45.4 dB SNDR for 50 MHz and 100 MHz bandwidths, while dissipating 116 mW of power.
13 citations
References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
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TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
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TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
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TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
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01 Mar 1993TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations