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Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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01 Sep 2014
TL;DR: An analysis of the maximum clock rate of continuous-time ΔΣ modulators when limited by the metastability error of the internal flash ADC is presented, resulting in a simple relationship between metastable error and SNR.
Abstract: The maximum clock rate of continuous-time ΔΣ modulators has increased dramatically over the past several years, showing that continuous-time systems can operate at higher rates than their discrete-time counterparts. This paper outlines the circuits and architectures that have led to these improvements and presents an analysis of the maximum clock rate of continuous-time ΔΣ modulators when limited by the metastability error of the internal flash ADC, resulting in a simple relationship between metastability error and SNR. A circuit simulation technique is also presented that helps analyse high-speed continuous-time systems to identify and correct non-idealities in the modulator's transfer functions.
12 citations
TL;DR: This paper presents a rigorous mathematical analysis of DDSMs with LFSR-based pseudorandom dither, and a design methodology to achieve effectively masked dithering.
Abstract: Digital delta-sigma modulators (DDSMs) are finite state machines; their spectra are characterized by strong periodic tones (so-called spurs) when they cycle repeatedly in time through a small number of states. This is particularly likely to happen when the input is constant or periodic. Dither generators based on linear feedback shift registers (LFSRs) are widely used to break up periodic cycles in DDSMs in order to eliminate spurs produced by underlying periodic behavior. Unfortunately, pseudorandom dither signals produced by LFSRs are themselves periodic and therefore may have limited effectiveness. This paper presents a rigorous mathematical analysis of DDSMs with LFSR-based pseudorandom dither, and a design methodology to achieve effectively masked dithering.
12 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...In a DDSM, a high resolution discrete-time input is oversampled and requantized to produce a lower resolution output [2]....
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TL;DR: A Vector Impedance Analyser architecture specifically devised to be interfaced with an array of impedimetric sensors for environmental applications, such as distributed water monitoring, or for mobile-Health/wearable biomedical devices is presented.
12 citations
TL;DR: An integrated analog pulse compressor for a multiple-input multiple-output (MIMO) radar has been developed with an 0.18-¿m CMOS process using an arbitrary waveform generator, analog correlators, and analog-to-digital converters, and the identification of overlapping multiple chirp signals is successfully demonstrated.
Abstract: Conventional radar pulse compressors use either surface acoustic wave devices or fast convolution processing, but both solutions have significant drawbacks. To overcome these drawbacks, an integrated analog pulse compressor for a multiple-input multiple-output (MIMO) radar has been developed with an 0.18-?m CMOS process using an arbitrary waveform generator, analog correlators, and analog-to-digital converters. The proposed scheme not only has advantages over conventional methods but also adds additional flexibility to the MIMO system. The die area is 5.67 mm2, and the power consumption is 62.6 mW from the 1.8-V supply. Arbitrary waveforms such as the wavelet and the chirp signal have been demonstrated, and the average signal-to-noise ratio for the pulse compression is 18.09 dB. The identification of overlapping multiple chirp signals is successfully demonstrated.
12 citations
01 Nov 2011
TL;DR: A second-order audio sigma-delta modulator has been implemented in 40nm CMOS with 0.05mm2 thickness and measured results show 90dB SNDR, 98dB THD, and 102dB dynamic range with-in 24kHz bandwidth, while consuming 500μW of total power at 6.5MHz sampling.
Abstract: A second-order audio sigma-delta modulator has been implemented in 40nm CMOS with 0.05mm2. Hybrid mode operation with comparator reduction technology is designed under optimized system synthesis model. DAC element selection with positive and negative state scrambling is provided in the design. A start-up sequence including RC calibration and signal monitoring is developed to prevent unstable operation. The measured results show 90dB SNDR, 98dB THD, and 102dB dynamic range with-in 24kHz bandwidth, while consuming 500μW of total power at 6.5MHz sampling.
12 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...The FOM [3], which is equal to DRdB+10log* (bandwidth/power), is summarized in Table I. IV....
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...The FOM [3], which is equal to DRdB+10log* (bandwidth/power), is summarized in Table I....
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...The FOM and area comparison among audioband application shows highly optimized performance of the presented modulator....
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References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations