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Understanding Delta-Sigma Data Converters

TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

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Citations
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Journal ArticleDOI
Sujin Park1, Geon-Hwi Lee1, SeongHwan Cho1
TL;DR: This paper presents a sensor front end for air pressure sensor, relative humidity (RH) sensor, and accelerometer in a standard CMOS process, equipped with a wide input range high-resolution capacitance-to-digital converter (CDC).
Abstract: This paper presents a sensor front end for air pressure sensor, relative humidity (RH) sensor, and accelerometer in a standard CMOS process, equipped with a wide input range high-resolution capacitance-to-digital converter (CDC). For air pressure and RH, interdigitated top metals in air and polyimide are exploited, respectively, which exhibit the change in dielectric constant. For acceleration, separation among three bondwires is exploited. These sensing transducers induce capacitance change that is quantized by a CDC based on a dual-quantization architecture that employs a single-bit first-order $\Delta \Sigma $ modulator and a 7-bit SAR analog-to-digital converter (ADC). Implemented in 0.18- $\mu \text{m}$ CMOS, the air pressure sensor, RH sensor, and accelerometer achieve a noise floor of 0.14 psi/ $\sqrt {\textrm {Hz}}$ , 0.001 %RH/ $\sqrt {\textrm {Hz}}$ , and 4.6 mg/ $\sqrt {\textrm {Hz}}$ , respectively. The CDC achieves a resolution of 864 aF (minimum resolution of 116 aF) when the sensing capacitance is 10 pF and consumes $3~\mu \text{W}$ from 1.1-V supply.

12 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...The dead-zone around a zero input is the widest, and its range is approximately 1/A where A is the dc gain of amplifier [43]....

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MonographDOI
07 Jan 2014
TL;DR: A general biomedical device comprises energy source, analog-to-digital conversion (ADC), digital signal processing, and digital signal Processing (DSP) for biomedical electronics.
Abstract: Biomedical electronics has gained significant attention in healthcare A general biomedical device comprises energy source, analog-to-digital conversion (ADC), digital signal processing, and commun

12 citations

Journal ArticleDOI
TL;DR: It is found that finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the architecture.
Abstract: In this brief, single-path time-interleaved delta-sigma modulators are analyzed and evaluated. It is found that finite opamp gain and bandwidth result in a mismatch between the noise transfer functions of the internal quantizers which degrades the performance of the architecture. A hybrid topology where the first stage uses multiple integrators while the rest of the modulator uses a single path of integrators is proposed to mitigate the mismatch problem.

12 citations


Cites background from "Understanding Delta-Sigma Data Conv..."

  • ...2 [6] is compared to a traditional second-order cascade of integrators with feedback (CIFB) modulator [11] and the MPTI modulator shown in Fig....

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Journal ArticleDOI
TL;DR: The proposed method reduces the in-band aliasing signals of the four-channel TI-ADCs by using in-phase/quadrature-phase (I/Q) downconversion mixers, cascaded integrator-comb (CIC) filters, and automatic gain control (AGC) in the receiver.
Abstract: Time-interleaving analog-to-digital converters (ADCs) decrease the required sampling rate for one ADC to achieve giga samples per second (GS/s) rates. The gain and timing mismatches among the ADCs generate aliasing signals, degrading the spurious-free dynamic range of the time-interleaved ADC (TI-ADC). The conventional digital correction methods for TI-ADCs have not considered an application to direct-radio-frequency (RF) sampling receivers. We present a digital correction method for bandpass sampling four-channel TI-ADCs in the receivers. The proposed method, based on a correction method for two-channel TI-ADCs, reduces the in-band aliasing signals of the four-channel TI-ADCs by using in-phase/quadrature-phase (I/Q) downconversion mixers, cascaded integrator-comb (CIC) filters, and automatic gain control (AGC) in the receiver. This allows the correction circuit including mismatch estimation to have fewer building blocks than the conventional methods: seven adders, seven multipliers, and no finite-impulse-response filters. Simulations and measurements show that the proposed method reduces the aliasing signals of 1.2 GS/s 12-bit four-channel TI-ADCs to less than −80 dBFS.

12 citations

Journal ArticleDOI
TL;DR: Though the influence of varying environmental conditions on the stability of repeated PUF readouts is negligible, inevitable deviations in the correction coefficients increase the intra-Hamming distance with respect to nominal conditions, and 80 highly stable identification bits are obtained from the exemplarily used ∆Σ modulator.
Abstract: This paper presents a novel approach of deriving Physical Unclonable Functions (PUF) from correction circuits measuring and digitizing non-linearities of data converters. The often digitally available correction data can then be used to generate a fingerprint of the chip. The general concept is presented and then specifically evaluated on an existing Delta-Sigma (∆Σ) modulator whose outermost feedback DAC mismatches are greatly influencing the overall performance and thus need correction. The applied mixed-signal correction scheme reveals the intrinsic mismatches which are firstly used to linearize the ∆Σ modulator, but which can also be further analyzed. The intraHamming distance is initially determined to values less than 6% at nominal conditions and could be further reduced to less than 2% by applying different encodings. Regarding the distinctness of devices, the inter-Hamming distance is highly stable under all circumstances with a value very close to 50%. Though the influence of varying environmental conditions on the stability of repeated PUF readouts is negligible, inevitable deviations in the correction coefficients increase the intra-Hamming distance with respect to nominal conditions. As a result, 80 highly stable identification bits are obtained from the exemplarily used ∆Σ modulator. Keywords—Physical unclonable function (PUF), DAC linearization, delta sigma modulation

12 citations

References
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Journal ArticleDOI
TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >

399 citations

Journal ArticleDOI
James C. Candy1
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.

342 citations

Journal ArticleDOI
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.

284 citations

Book ChapterDOI
James C. Candy1, O. Benjamin1
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.

255 citations

Journal ArticleDOI
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >

211 citations