Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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TL;DR: Results from a prototype current-DAC driven by a VHDL simulation of the digital design at 2.66 GHz show that 56-dB linearity is achievable in 90-nm CMOS within a 1-V supply over a 155-MHz signal bandwidth making the architecture suitable for emerging ultra-wide-band and 60-GHz radio applications.
Abstract: This paper describes a delta-sigma (DeltaSigma) digital-to-analog converter (DAC) architecture that combines a polyphase decomposition of the interpolation filter and a time-interleaved error-feedback DeltaSigma modulator. Noise-shaped oversampling is achieved while clocking the digital circuitry at the Nyquist rate. The design of a third-order 4-bit modulator with eight times oversampling using the architecture is presented. Results from a prototype current-DAC driven by a VHDL simulation of the digital design at 2.66 GHz show that 56-dB linearity is achievable in 90-nm CMOS within a 1-V supply over a 155-MHz signal bandwidth making the architecture suitable for emerging ultra-wide-band and 60-GHz radio applications.
11 citations
24 Jun 2015
TL;DR: This work presents guidelines for the design of an on-chip ramp signal generator for static Built-In Self-Test (BIST) of ADCs based on a fully-differential switched-capacitor integrator conveniently modified to produce a very small integration gain.
Abstract: This work presents guidelines for the design of an on-chip ramp signal generator for static Built-In Self-Test (BIST) of ADCs. The proposed ramp generator is based on a fully-differential switched-capacitor (SC) integrator conveniently modified to produce a very small integration gain. The main non-idealities affecting the linearity of the generator are discussed on a practical implementation in a 65nm CMOS technology. Electrical simulation results at transistor level are provided to verify the feasibility and performance of the proposed approach.
11 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...4) Noise: In the presence of noise, the Z-transform of a single-ended integrator output voltage can be expressed as [11], [12],...
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...It can be demonstrated [11], [12] that the equivalent input noise voltage for the integrator, integrated from 0 to Tclk/2, can be expressed as...
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TL;DR: This paper describes a very-high-speed integrated-circuit hardware description language (VHDL)-based analog-node model, an associated driver component for the mixed-signal event-driven (MixED) simulation technique, and some primitive device models applied to radio-frequency integrated circuits.
Abstract: This paper describes a very-high-speed integrated-circuit hardware description language (VHDL)-based analog-node model, an associated driver component for the mixed-signal event-driven (MixED) simulation technique, and some primitive device models applied to radio-frequency integrated circuits. With the presented MixED method, analog circuits are modeled as a composition of controlled sources. Unlike other VHDL-based analog simulation methods, these MixED sources compute not only a real number representing an output voltage but also an output impedance. This allows the outputs of several MiXED sources to be connected in order to drive the same node signal n . The voltage of this record-type signal is automatically computed at its element n.u by resolution functions in compliance with Kirchhoff's current law. The data structure of the node signal n, its self-defined resolution functions, and an associated driver component are presented and discussed to meet different simulation requirements, such as speed, versatility, current accuracy, and adaptive time stepping. Several examples demonstrate how to behaviorally model mixed-signal components with this method with an emphasis on the simulation of a heterodyne receiver. Simulation speeds are compared to VHDL-AMS tools.
11 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...14 using DEM without the smoothing capacitor was simulated with the MixED VHDL library and the testcode shown in Fig....
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...Dynamic element matching (DEM) [54], [55] scrambles the high drivers....
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...DEM is particularly useful in combination with oversampling devices, such as delta-sigma DACs [54], which are frequently used in RF transceivers....
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24 May 2010
TL;DR: In this paper, a DFIG base wind turbine generation system proposed, in which its common back-to-back converter replaced with an indirect matrix converter (IMC) that uses Sigma-Delta (ΣΔ) modulator to control switches matrix.
Abstract: The conventional type of DFIG system has some drawbacks mainly due to large DC link capacitor. Existence of this capacitor causes converter average lifetime and reliability of system reduction, and maintenance cost proliferation. In this paper a DFIG base wind turbine generation system proposed, in which its common back-to-back converter replaced with an indirect matrix converter (IMC) that uses Sigma-Delta (ΣΔ) modulator to control switches matrix. In this system DC link capacitor is omitted, so system gets more reliable performance and it is cost effective. Furthermore by using ΣΔ modulator IMC performances enhanced. Therefore due to generated current THD reduction, pulsative torque of system reduces that has undeniable effect on mechanical system lifetime. Besides THD of output current wind turbine reduces, that improves power quality of generated power.
11 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...Recently‚ oversampled modulators have received a many attention for highresolution data conversion applications‚ such as highquality digital audio‚ instrumentation and measurement‚ and sensor applications [11]....
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TL;DR: An apparatus for the simultaneous measurement of the Seebeck coefficient and electrical resistance of bulk and thin-film samples using zero current measurement technique is presented, which automatically measures these quantities at different temperature profiles at steady-state, quasi-steady- state, and transient conditions in different atmospheres.
Abstract: The main challenge in thermoelectric metrology is an accurate Seebeck coefficient measurement on high electrical resistance bulk and thin-film samples, as the loading by the measuring device causes a considerable voltage drop on the internal resistance of the sample. It has been shown that this technical problem can be solved by utilizing the zero current technique of measurement. Here, an apparatus for the simultaneous measurement of the Seebeck coefficient and electrical resistance of bulk and thin-film samples using zero current measurement technique is presented, which automatically measures these quantities at different temperature profiles at steady-state, quasi-steady-state, and transient conditions in different atmospheres. Thick-film tin oxide microheaters are utilized to provide the desired temperature gradient along with the sample from room temperature up to 1200 K, and zero current method is used to eliminate errors originating from the high internal resistance of the sample. As examples, Seebeck voltages and electrical resistances are measured on the bulk and thin-film zinc oxide samples with internal resistances in the megohm ( $\text{M}\Omega$ ) range. Operating the device for measurements involving time-varying temperature gradients is demonstrated.
11 citations
References
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TL;DR: Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering.
Abstract: Oversampling interpolative coding has been demonstrated to be an effective technique for high-resolution analog-to-digital (A/D) conversion that is tolerant of process imperfections. A novel topology for constructing stable interpolative modulators of arbitrary order is described. Analysis of this topology shows that with proper design of the modulator coefficients, stability is not a limitation to higher order modulators. Furthermore, complete control over placement of the poles and zeros of the quantization noise response allows treatment of the modulation process as a high-pass filter for quantization noise. Higher order modulators are shown not only to greatly reduce oversampling requirements for high-resolution conversion applications, but also to randomize the quantization noise, avoiding the need for dithering. An experimental fourth-order modulator breadboard demonstrates stability and feasibility, achieving a 90-dB dynamic range over the 20-kHz audio bandwidth with a sampling rate of 2.1 MHz. A generalized simulation software package has been developed to mimic time-domain behavior for oversampling modulators. Circuit design specifications for integrated circuit implementation can be deduced from analysis of simulated data. >
399 citations
TL;DR: It is shown that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio.
Abstract: Decimation is an important component of oversampled analog-to-digital conversion. It transforms the digitally modulated signal from short words occurring at high sampling rate to longer words at the Nyquist rate. Here we are concerned with the initial stage of decimation, where the word rate decreases to about four times the Nyquist rate. We show that digital filters comprising cascades of integrate-and-dump functions can match the structure of the noise from sigma delta modulation to provide decimation with negligible loss of signal-to-noise ratio. Explicit formulas evaluate particular tradeoffs between modulation rate, signal-to-noise ratio, length of digital words, and complexity of the modulating and decimating functions.
342 citations
TL;DR: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion, followed by an additive noise source representing distortion components.
Abstract: This paper introduces a new method of analysis for deltasigma modulators based on modeling the nonlinear quantizer with a linearized gain, obtained by minimizing a mean-square-error criterion [7], followed by an additive noise source representing distortion components. In the paper, input signal amplitude dependencies of delta-sigma modulator stability and signal-to-noise ratio are analyzed. It is shown that due to the nonlinearity of the quantizer, the signal-to-noise ratio of the modulator may decrease as the input amplitude increases prior to saturation. Also, a stable third-order delta-sigma modulator may become unstable by increasing the input amplitude beyond a certain threshold. Both of these phenomena are explained by the nonlinear analysis of this paper. The analysis is carried out for both dc and sinusoidal excitations.
284 citations
TL;DR: Simple algebraic expressions for this modulation noise and its spectrum in terms of the input amplitude are derived and can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
Abstract: When the sampling rate of a sigma-delta modulator far exceeds the frequencies of the input signal, its modulation noise is highly correlated with the amplitude of the input. We derive simple algebraic expressions for this noise and its spectrum in terms of the input amplitude. The results agree with measurements taken on a breadboard circuit. This work can be useful for designing oversampled analog to digital converters that use sigma-delta modulation for the primary conversion.
255 citations
01 Mar 1993
TL;DR: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter.
Abstract: The modulator of a bandpass analog/digital (A/D) converter, with 63 dB signal/noise for broadcast AM bandwidth signals centered at 455 kHz, has been implemented by modifying a commercial digital-audio sigma-delta ( Sigma Delta ) converter. It is the first reported fully monolithic implementation of bandpass noise shaping and has applications to digital radio. >
211 citations