Book•
Understanding Delta-Sigma Data Converters
08 Nov 2004-
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.
Citations
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TL;DR: This paper offers the first in-depth look at the vast applications of THz wireless products and applications and provides approaches for how to reduce power and increase performance across several problem domains, giving early evidence that THz techniques are compelling and available for future wireless communications.
Abstract: Frequencies from 100 GHz to 3 THz are promising bands for the next generation of wireless communication systems because of the wide swaths of unused and unexplored spectrum. These frequencies also offer the potential for revolutionary applications that will be made possible by new thinking, and advances in devices, circuits, software, signal processing, and systems. This paper describes many of the technical challenges and opportunities for wireless communication and sensing applications above 100 GHz, and presents a number of promising discoveries, novel approaches, and recent results that will aid in the development and implementation of the sixth generation (6G) of wireless networks, and beyond. This paper shows recent regulatory and standard body rulings that are anticipating wireless products and services above 100 GHz and illustrates the viability of wireless cognition, hyper-accurate position location, sensing, and imaging. This paper also presents approaches and results that show how long distance mobile communications will be supported to above 800 GHz since the antenna gains are able to overcome air-induced attenuation, and present methods that reduce the computational complexity and simplify the signal processing used in adaptive antenna arrays, by exploiting the Special Theory of Relativity to create a cone of silence in over-sampled antenna arrays that improve performance for digital phased array antennas. Also, new results that give insights into power efficient beam steering algorithms, and new propagation and partition loss models above 100 GHz are given, and promising imaging, array processing, and position location results are presented. The implementation of spatial consistency at THz frequencies, an important component of channel modeling that considers minute changes and correlations over space, is also discussed. This paper offers the first in-depth look at the vast applications of THz wireless products and applications and provides approaches for how to reduce power and increase performance across several problem domains, giving early evidence that THz techniques are compelling and available for future wireless communications.
1,352 citations
Proceedings Article•
06 Dec 2017
TL;DR: Quantized SGD (QSGD) as discussed by the authors is a family of compression schemes for gradient updates which provides convergence guarantees for convex and nonconvex objectives, under asynchrony, and can be extended to stochastic variance-reduced techniques.
Abstract: Parallel implementations of stochastic gradient descent (SGD) have received significant research attention, thanks to its excellent scalability properties. A fundamental barrier when parallelizing SGD is the high bandwidth cost of communicating gradient updates between nodes; consequently, several lossy compresion heuristics have been proposed, by which nodes only communicate quantized gradients. Although effective in practice, these heuristics do not always guarantee convergence, and it is not clear whether they can be improved. In this paper, we propose Quantized SGD (QSGD), a family of compression schemes for gradient updates which provides convergence guarantees. QSGD allows the user to smoothly trade off \emph{communication bandwidth} and \emph{convergence time}: nodes can adjust the number of bits sent per iteration, at the cost of possibly higher variance. We show that this trade-off is inherent, in the sense that improving it past some threshold would violate information-theoretic lower bounds. QSGD guarantees convergence for convex and non-convex objectives, under asynchrony, and can be extended to stochastic variance-reduced techniques. When applied to training deep neural networks for image classification and automated speech recognition, QSGD leads to significant reductions in end-to-end training time. For example, on 16GPUs, we can train the ResNet152 network to full accuracy on ImageNet 1.8x faster than the full-precision variant.
759 citations
17 Nov 2008
TL;DR: This paper summarizes recent trends in the area of low-power A/D conversion and a discussion on minimalistic and digitally assisted design approaches is used to sketch a route toward further improvements in ADC power efficiency and performance.
Abstract: This paper summarizes recent trends in the area of low-power A/D conversion. Survey data collected over the past eleven years indicates that the power efficiency of ADCs has improved on average by a factor of two every two years. A closer inspection on the impact of technology scaling is presented to explain the observed trend in the context of shrinking supply voltages and increasing device speed. Finally, a discussion on minimalistic and digitally assisted design approaches is used to sketch a route toward further improvements in ADC power efficiency and performance.
292 citations
TL;DR: A tutorial description of the physical phenomena taking place in an SC circuit while it processes noise is provided and some specialized but highly efficient algorithms for estimating the resulting sampled noise in SC circuits are proposed, which need only simple calculations.
Abstract: Thermal noise represents a major limitation on the performance of most electronic circuits. It is particularly important in switched circuits, such as the switched-capacitor (SC) filters widely used in mixed-mode CMOS integrated circuits. In these circuits, switching introduces a boost in the power spectral density of the thermal noise due to aliasing. Unfortunately, even though the theory of noise in SC circuits is discussed in the literature, it is very intricate. The numerical calculation of noise in switched circuits is very tedious, and requires highly sophisticated and not widely available software. The purpose of this paper is twofold. It provides a tutorial description of the physical phenomena taking place in an SC circuit while it processes noise (Sections II-III). It also proposes some specialized but highly efficient algorithms for estimating the resulting sampled noise in SC circuits, which need only simple calculations (Sections IV-VI ). A practical design procedure, which follows directly from the estimate, is also described. The accuracy of the proposed estimation algorithms is verified by simulation using SpectreRF. As an example, it is applied to the estimation of the total thermal noise in a second-order low-distortion delta-sigma converter.
262 citations
Cites background from "Understanding Delta-Sigma Data Conv..."
...More detailed discussion of some issues mentioned in this paper can be found in [4] and [5]....
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...Assigning 75% of the noise power to thermal noise [4], the total permissible input-referred thermal noise power turns out to be...
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Posted Content•
TL;DR: This work investigates massive multiple-input-multiple output (MIMO) uplink systems with 1-bit analog-to-digital converters (ADCs) on each receiver antenna with good performance in terms of mutual information and symbol error rate (SER), and provides an analytical approach to calculate the Mutual information and SER of the MRC receiver.
Abstract: We investigate massive multiple-input-multiple output (MIMO) uplink systems with 1-bit analog-to-digital converters (ADCs) on each receiver antenna. Receivers that rely on 1-bit ADC do not need energy-consuming interfaces such as automatic gain control (AGC). This decreases both ADC building and operational costs. Our design is based on maximal ratio combining (MRC), zero-forcing (ZF), and least squares (LS) detection, taking into account the effects of the 1-bit ADC on channel estimation. Through numerical results, we show good performance of the system in terms of mutual information and symbol error rate (SER). Furthermore, we provide an analytical approach to calculate the mutual information and SER of the MRC receiver. The analytical approach reduces complexity in the sense that a symbol and channel noise vectors Monte Carlo simulation is avoided.
251 citations
References
More filters
TL;DR: A new kind of sigma-delta modulator made with a double integrator and a bandpass stage is presented that can reduce the oversampling ratio or increase the bandwidth for a constant sampling frequency compared with equivalent complexity modulators.
Abstract: A new kind of sigma-delta modulator made with a double integrator and a bandpass stage is presented. It can reduce the oversampling ratio or increase the bandwidth for a constant sampling frequency compared with equivalent complexity modulators.
36 citations
01 Feb 1995
TL;DR: In this article, the authors present a list of Symbols and Symbols for Symbols, including the following symbols and their meanings: http://www.symbolic-semantics.org/
Abstract: xv List of Symbols xvi
31 citations
11 Jun 1991
TL;DR: In this paper, a framework for stability analysis of Sigma-Delta modulators is proposed, and a number of analytical and approximate techniques to aid the stability analysis are presented. But these techniques do not explicitly take stability into account.
Abstract: A framework is suggested for stability analysis of Sigma - Delta modulators. The authors argue that limit cycles are natural quantities to investigate in this context. They present a number of analytical and approximate techniques to aid the stability analysis of the class of interpolative modulators, and use these to propose a way of improved design which explicitly takes stability into account. >
29 citations
Book•
31 Oct 1999
TL;DR: This paper presents an algorithm for Finding a Stability Boundary for Continuous time Bandpass SDMs and its applications in Quantization and Sampling, and a implementation of this algorithm in a digital SDM.
Abstract: Preface. 1. Introduction. 2. Quantization and Sampling. 3. Noise Shaping Concepts. 4. Performance. 5. Stability. 6. Design of Continuous time Bandpass SDMs. 7. SDM Implementations. 8. Conclusion and Discussion. References. List of Acronyms. List of Symbols. A. Modulator Response to Input Signals. B. Root Locus Search Method. C. Algorithm for Finding a Stability Boundary. D. Example VHDL description of a digital SDM. About the Authors. Index.
28 citations
01 Jan 1999
TL;DR: Novel techniques for multi-bit oversampled data conversion are described, and several types of scaled-element mismatch-shaping D/A converters are proposed that can yield 100 dB performance at 10 times oversampling.
Abstract: Novel techniques for multi-bit oversampled data conversion are described. State-of-the-art oversampled data converters are analyzed, leading to the conclusion that their performance is limited mainly by low-resolution signal representation. To increase the resolution, high-performance, high-resolution internal D/A converters are required. Unit-element mismatch-shaping D/A converters are analyzed, and the concept of mismatch-shaping is generalized to include scaled-element D/A converters. Several types of scaled-element mismatch-shaping D/A converters are proposed. Simulations show that, when implemented in a standard CMOS technology, they can be designed to yield 100 dB performance at 10 times oversampling. The proposed scaled-element mismatch-shaping D/A converters are well suited for use as the feedback stage in oversampled delta-sigma quantizers. It is, however, not easy to make full use of their potential, because that requires a high-resolution loop quantizer which introduces only a small delay. Generally, it is not acceptable to design the loop quantizer as a high-resolution flash quantizer because they require a large chip area and high power consumption. Pipeline techniques are proposed to circumvent this problem. This way, the delta-sigma quantizer’s feedback signal is obtained by a multiple-stage quantization, where the loop quantizer (low-resolution and minimum-delay) implements only the last-stage quantization. Hence, high-speed, high-resolution delta-sigma quantization is feasible without using complex circuitry. An improved version of the MASH topology is also proposed. A delta-sigma quantizer is used to quantize the input signal into an oversampled digital representation of low-to-moderate resolution. The deltai
27 citations