Universal fault diagnosis for lookup table FPGAs
Citations
156 citations
Cites methods from "Universal fault diagnosis for looku..."
...While FPGA testing has been the focus of many recent papers [6][8][11][12][ 13 ][14][17][21][23][24][30][31][32] [33], most of the previous work deals with off-line testing, which is not applicable in missions relying on continuous system operation....
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131 citations
Cites methods from "Universal fault diagnosis for looku..."
...A number of testing methods have been proposed for particular FPGA architectures (e.g., [ 10 , 11, 12, 13]), as well as many FPGA architectures designed with DFT considerations in mind [14, 15]....
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127 citations
Cites background or methods from "Universal fault diagnosis for looku..."
...Methods that did provide complete tests for configuration multiplexers, such as [21] and [19], used models that did not remove the invisible logic....
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...The time of the method described in [21] does not depend on , but this is based on a parallel loading mechanism that is not featured in existing FPGAs....
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...2 illustrates the typical structure of a PLB, consisting of memory block that can function as a look-up table (LUT) or RAM, several flip–flops (FFs), and multiplexing output logic....
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125 citations
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References
258 citations
Additional excerpts
...TSL S (DPC) = (4kn + 24 + 8 + 32)ts = O(n log n) (7)...
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Additional excerpts
...TSL S (DP1) = [4kn + (2N + 10) + 8 + (4N + 12)]ts = O(N + n log n) (5)...
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60 citations
"Universal fault diagnosis for looku..." refers background in this paper
...(2) Now, let’s consider DP’s universal diagnosis complexity for SL-FPGAs....
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