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Journal ArticleDOI

Universal fault diagnosis for lookup table FPGAs

01 Jan 1998-IEEE Design & Test of Computers (IEEE Computer Society Press)-Vol. 15, Iss: 1, pp 39-44
TL;DR: Focusing on configurable logic blocks in a lookup table FPGA, the authors present universal fault diagnosis procedures that can locate a fault to just one CLB.
Abstract: Focusing on configurable logic blocks in a lookup table FPGA, the authors present universal fault diagnosis procedures that can locate a fault to just one CLB. The complexity of the proposed procedure for FPGAs using block-sliced loading is independent of FPGA array size.
Citations
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Proceedings ArticleDOI
28 Sep 1999
TL;DR: A new fault-tolerant (FT) technique allows using partially defective FPGA resources for normal operation, providing longer mission life-span in the presence of faults, and the basic concepts of a new dynamic FT method are introduced.
Abstract: In this paper we present a novel integrated approach to on-line FPGA testing, diagnosis, and fault-tolerance, to be used in high-reliability and high-availability hardware. The test process takes place in self-testing areas (STARs) of the FPGA, without disturbing the normal system operation. The entire chip is eventually tested by having (STARs) gradually rove across the FPGA. Our approach guarantees complete testing of programmable logic blocks and interconnect, and provides maximum diagnostic resolution. A new fault-tolerant (FT) technique allows using partially defective FPGA resources for normal operation, providing longer mission life-span in the presence of faults. We also introduce the basic concepts of a new dynamic FT method, spare resources needed to bypass a fault are always in the neighborhood of the located fault, thus simplifying fault-bypassing.

156 citations


Cites methods from "Universal fault diagnosis for looku..."

  • ...While FPGA testing has been the focus of many recent papers [6][8][11][12][ 13 ][14][17][21][23][24][30][31][32] [33], most of the previous work deals with off-line testing, which is not applicable in missions relying on continuous system operation....

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Book ChapterDOI
30 Sep 2003
TL;DR: In this paper, a defect tolerance methodology centered around reconfigurable devices, a scalable testing method, and dynamic place-and-route has been proposed for nanometer-scale computing.
Abstract: As feature sizes shrink closer to single digit nanometer dimensions, defect tolerance will become increasingly important. This is true whether the chips are manufactured using top-down methods, such as photolithography, or bottom-up assembly processes such as Chemically Assembled Electronic Nanotechnology (CAEN). In this chapter, we examine the consequences of this increased rate of defects, and describe a defect tolerance methodology centered around reconfigurable devices, a scalable testing method, and dynamic place-and-route. We summarize some of our own results in this area as well as those of others, and enumerate some future research directions required to make nanometer-scale computing a reality.

131 citations


Cites methods from "Universal fault diagnosis for looku..."

  • ...A number of testing methods have been proposed for particular FPGA architectures (e.g., [ 10 , 11, 12, 13]), as well as many FPGA architectures designed with DFT considerations in mind [14, 15]....

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Proceedings Article
01 Jan 2001
TL;DR: This work introduces the first diagnosis method for multiple faulty PLBs; for any faulty PLB, it is introduced its internal faulty modules or modes of operation and provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems.
Abstract: We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.

127 citations


Cites background or methods from "Universal fault diagnosis for looku..."

  • ...Methods that did provide complete tests for configuration multiplexers, such as [21] and [19], used models that did not remove the invisible logic....

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  • ...The time of the method described in [21] does not depend on , but this is based on a parallel loading mechanism that is not featured in existing FPGAs....

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  • ...2 illustrates the typical structure of a PLB, consisting of memory block that can function as a look-up table (LUT) or RAM, several flip–flops (FFs), and multiplexing output logic....

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Journal ArticleDOI
TL;DR: In this article, the authors present a built-in self-test (BIST) approach able to diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution.
Abstract: We present a built-in self-test (BIST) approach able to detect and accurately diagnose all single and practically all multiple faulty programmable logic blocks (PLBs) in field programmable gate arrays (FPGAs) with maximum diagnostic resolution. Unlike conventional BIST, FPGA BIST does not involve any area overhead or performance degradation. We also identify and solve the problem of testing configuration multiplexers that was either ignored or incorrectly solved in most previous work. We introduce the first diagnosis method for multiple faulty PLBs; for any faulty PLB, we also identify its internal faulty modules or modes of operation. Our accurate diagnosis provides the basis for both failure analysis used for yield improvement and for any repair strategy used for fault-tolerance in reconfigurable systems. We present experimental results showing detection and identification of faulty PLBs in actual defective FPGAs. Our BIST architecture is easily scalable.

125 citations

Journal ArticleDOI
TL;DR: A systematic approach consisting in a set of lookup tables generated from IC and PA techniques providing a simple, fast, and accurate automated estimation of LIB degradation modes to be implemented in BMSs is presented.
Abstract: Lithium-ion battery (LIB) degradation originates from complex mechanisms, usually interacting simultaneously in various degrees of intensity. Due to its complexity, to date, identifying battery aging mechanisms remains challenging. Recent improvements in battery degradation identification have been developed, including validated, in situ incremental capacity (IC) and peak area (PA) analysis. Due to their in situ and non-destructive nature, IC and PA implementation is feasible in on-board battery management systems (BMSs). Despite their advantages, the understanding and applicability of IC and PA techniques is not straightforward, as it requires both electrochemical and material science backgrounds. However, BMS design teams are mainly integrated by electrical engineers and may not include battery scientists. Aiming to bridge gaps in knowledge between electrical engineering and battery science toward battery degradation identification, here we present a systematic approach consisting in a set of lookup tables generated from IC and PA techniques. The lookup tables provide a simple, yet reliable, tool for the evaluation of LIB degradation modes. Various real-life examples of cell degradation are also presented to illustrate and validate the use of the proposed approach. This study exemplifies the use of lookup tables providing a simple, fast, and accurate automated estimation of LIB degradation modes to be implemented in BMSs.

95 citations

References
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Journal ArticleDOI
TL;DR: Property of systems that enable them to be tested with a fixed constant number of tests independent of p, the number of cells in the system are considered, referred to as C-testable.
Abstract: It has been shown that the number of tests required to detect all faults in a one-dimensional unilateral combinational iterative array consisting of p cells will, in general, be proportional to p. In this paper we consider properties of such systems that enable them to be tested with a fixed constant number of tests independent of p, the number of cells in the system. Such systems are referred to as C-testable. Necessary and sufficient conditions on the basic cell state table are derived for an iterative system to be C-testable. It is shown that an arbitrary N-state cell table can be augmented by the addition of, at most, one row and less than [log2 N]2 columns (for N ≥ 2) so as to be C-testable.

258 citations


Additional excerpts

  • ...TSL S (DPC) = (4kn + 24 + 8 + 32)ts = O(n log n) (7)...

    [...]

Proceedings ArticleDOI
27 Apr 1997
TL;DR: A methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices is proposed and it is demonstrated that a set of only 3 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant.
Abstract: This paper proposes a methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices. Two different approaches with different objectives are identified: the Manufacturing Test Procedure and the User Test Procedure. The proposed method is used to generate a Manufacturing Test Procedure targeting the Interconnect Structure of RAM-based FPGA. It is demonstrated that a set of only 3 Test Configurations called the Orthogonal, the Diagonal-1 and Diagonal-2 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant. Then the test of each configuration is shown equivalent to the test of classical buses. The final proposed Manufacturing Test Procedure present a constant number of Test Configurations (3) and very short Test Sequences.

116 citations

Proceedings ArticleDOI
28 Apr 1996
TL;DR: This paper presents a new general technique for testing field programmable gate arrays (FPGAs) by fully exploiting their programmable and configurable characteristics by introducing a hybrid fault model based on a physical and behavioral characterization.
Abstract: This paper presents a new general technique for testing field programmable gate arrays (FPGAs) by fully exploiting their programmable and configurable characteristics. A hybrid fault model is introduced based on a physical and behavioral characterization; this permits the detection of a single fault, as either a stuck-at or a functional fault. A general approach which regards testing as can application for the reconfigurable FPGA, is then proposed. It is shown that different arrangements of disjoint one-dimensional arrays with unilateral horizontal connections and common vertical input lines provide a very good solution. A further feature that is considered for array testing, is the relation between the configuration of the logic blocks and the number of I/O pins in the chip. As an example, the proposed approach is applied for testing the Xilinz 4000 family of FPGAs.

106 citations

Proceedings ArticleDOI
28 Apr 1996
TL;DR: It is shown that the proposed diagnostic technique can be applied to the general purpose interconnect of the FPGAs in the 3000 family by Xilinx.
Abstract: This paper considers the diagnosis of field programmable interconnect systems (FPIS) in which programmable grids made of switches are included. For this type of interconnects, the number of times the grid must be programmed and the programming sequence of the switches an two of the most important figures of merit for full diagnosis (defection and location with no aliasing and confounding). A hierarchical approach to diagnosis is proposed and fully characterized. The application of this technique to commercially available FPIS such as FPGAs, is discussed. It is shown that the proposed diagnostic technique can be applied to the general purpose interconnect of the FPGAs in the 3000 family by Xilinx.

62 citations


Additional excerpts

  • ...TSL S (DP1) = [4kn + (2N + 10) + 8 + (4N + 12)]ts = O(N + n log n) (5)...

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Proceedings ArticleDOI
23 Nov 1995
TL;DR: This paper proposes a programming scheme called block-sliced loading, which makes FPGAs C-testable, and presents two types of programming schemes; sequential loading and random access loading.
Abstract: A field-programmable gate array (FPGA) can implement arbitrary logic circuits in the field. In this paper we consider universal test such that when applied to an unprogrammed FPGA, it ensures that all the corresponding programmed logic circuits on the FPGA are fault-free. We focus on testing for look-up tables in FPGAs, and present two types of programming schemes; sequential loading and random access loading. Then we show test procedures for the FPGAs with these programming schemes and their test complexities. In order to make the test complexity for FPGAs independent of the array size of the FPGAs, we propose a programming scheme called block-sliced loading, which makes FPGAs C-testable.

60 citations


"Universal fault diagnosis for looku..." refers background in this paper

  • ...(2) Now, let’s consider DP’s universal diagnosis complexity for SL-FPGAs....

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