Upset hardened memory design for submicron CMOS technology
TL;DR: In this article, a design technique for storage elements which are insensitive to radiation-induced single-event upsets is proposed for implementation in high density ASICs and static RAMs using submicron CMOS technology.
Abstract: A novel design technique is proposed for storage elements which are insensitive to radiation-induced single-event upsets. This technique is suitable for implementation in high density ASICs and static RAMs using submicron CMOS technology.
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TL;DR: Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits as discussed by the authors, and the impact of technology trends on single event susceptibility and future areas of concern are explored.
Abstract: Physical mechanisms responsible for nondestructive single-event effects in digital microelectronics are reviewed, concentrating on silicon MOS devices and integrated circuits. A brief historical overview of single-event effects in space and terrestrial systems is given, and upset mechanisms in dynamic random access memories, static random access memories, and combinational logic are detailed. Techniques for mitigating single-event upset are described, as well as methods for predicting device and circuit single-event response using computer simulations. The impact of technology trends on single-event susceptibility and future areas of concern are explored.
1,028 citations
Additional excerpts
...Several design-hardened SRAM and latch circuits have been proposed and fabricated [108-113]....
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03 Dec 2003
TL;DR: This paper identifies numerous cases, such as prefetches, dynamicallydead code, and wrong-path instructions, in which a fault will not affect correct execution, and shows AVFs of 28% and 9% for the instruction queue and execution units, respectively,averaged across dynamic sections of the entire CPU2000benchmark suite.
Abstract: Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transients faults exist, but come at a cost. Designers clearly require accurate estimates of processor error rates to make appropriate cost/reliability tradeoffs. This paper describes a method for generating these estimates. A key aspect of this analysis is that some single-bit faults (such as those occurring in the branch predictor) do not produce an error in a program's output. We define a structure's architectural vulnerability factor (AVF) as the probability that a fault in that particular structure do not result in an error. A structure's error rate is the product of its raw error rate, as determined by process and circuit technology, and the AVF. Unfortunately, computing AVFs of complex structures, such as the instruction queue, can be quite involved. We identify numerous cases, such as prefetches, dynamically dead code, and wrong-path instructions, in which a fault do not affect, correct execution. We instrument a detailed 1A64 processor simulator to map bit-level microarchitectural state to these cases, generating per-structure AVF estimates. This analysis shows AVFs of 28% and 9% for the instruction queue and execution units, respectively, averaged across dynamic sections of the entire CPU2000 benchmark suite.
915 citations
Cites background from "Upset hardened memory design for su..."
...A device s error rate due to single event upsets depends on both the particle flux it encounters and its circuit characteristics....
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TL;DR: This article comprehensively analyzes soft-error sensitivity in modern systems and shows it to be application dependent.
Abstract: As the dimensions and operating voltages of computer electronics shrink to satisfy consumers' insatiable demand for higher density, greater functionality, and lower power consumption, sensitivity to radiation increases dramatically. In terrestrial applications, the predominant radiation issue is the soft error, whereby a single radiation event causes a data bit stored in a device to be corrupted until new data is written to that device. This article comprehensively analyzes soft-error sensitivity in modern systems and shows it to be application dependent. The discussion covers ground-level radiation mechanisms that have the most serious impact on circuit operation along with the effect of technology scaling on soft-error rates in memory and logic.
817 citations
26 Apr 1999
TL;DR: This work uses time redundancy techniques to derive low cost soft-error tolerant implementations for logic networks in response to the increased operating frequencies, geometry shrinking and power supply reduction that accompany the process of very deep submicron scaling.
Abstract: The increased operating frequencies, geometry shrinking and power supply reduction that accompany the process of very deep submicron scaling, affect the reliable operation of very deep submicron ICs. The effects of various noise sources are becoming of great concern. In particularly, it is predicted that single event upsets induced by alpha particles and cosmic radiation will become a cause of unacceptable error rates in future very deep submicron and nanometer technologies. This problem, concerning in the past more often parts used in space, will affect future ICs at sea level. This challenging problem has to be solved otherwise technological progress will be blocked soon. Thus, fault tolerant design is becoming necessary, even for commodity applications. But economic constraints of commodity applications exclude the use of traditional, high-cost fault tolerant techniques. This work uses time redundancy techniques to derive low cost soft-error tolerant implementations for logic networks.
528 citations
TL;DR: In this article, the Monte-Carlo simulator CORIMS was used to evaluate the soft-error rate of SRAMs from a 250 nm to a 22 nm process and found that the area affected by one nuclear reaction spreads over 1 M bits and bit multiplicity of multi-cell upset become as high as 100 bits and more.
Abstract: Trends in terrestrial neutron-induced soft-error in SRAMs from a 250 nm to a 22 nm process are reviewed and predicted using the Monte-Carlo simulator CORIMS, which is validated to have less than 20% variations from experimental soft-error data on 180-130 nm SRAMs in a wide variety of neutron fields like field tests at low and high altitudes and accelerator tests in LANSCE, TSL, and CYRIC. The following results are obtained: 1) Soft-error rates per device in SRAMs will increase x6-7 from 130 nm to 22 nm process; 2) As SRAM is scaled down to a smaller size, soft-error rate is dominated more significantly by low-energy neutrons (<; 10 MeV); and 3) The area affected by one nuclear reaction spreads over 1 M bits and bit multiplicity of multi-cell upset become as high as 100 bits and more.
437 citations
Cites background from "Upset hardened memory design for su..."
...cation [12], replication [13], and redundant-nodes latches/FFs [14]–[18] like the dual interlocked storage cell (DICE) [19]...
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...Typically redundancy circuits such as triple module redundancy (TMR) [11], duplication [12], replication [13], and redundant-nodes latches/FFs [14]–[18] like the dual interlocked storage cell (DICE) [19] cannot be effective when relevant nodes are corrupted simultaneously by an MCU [20], [21]....
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References
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Book•
01 Jan 1989TL;DR: In this article, Hughes et al. present a survey of the effects of radiation on MOS devices and circuits, including hardening technology, process-induced radiation effects, and interface traps.
Abstract: Historical Perspective (H. Hughes). Electron--Hole Generation, Transport, and Trapping in SiO2 (F. McLean, et al.). Radiation--Induced Interface Traps (P. Winokur). Radiation Effects on MOS Devices and Circuits (P. Dressendorfer). Radiation--Hardening Technology (P. Dressendorfer). Process--Induced Radiation Effects (T. Ma). Source Considerations and Testing Techniques (K. Kerris). Transient--Ionization and Single--Event Phenomena (S. Kerns). Index.
1,026 citations
TL;DR: In this paper, the authors present a simple method of calculating cosmic ray upset rates and compare the results of this method to results of an exact calculation and apply both methods to the prediction of upset rates as device feature sizes are scaled to submicron dimensions.
Abstract: Progression of VLSI circuitry to smaller feature sizes raises questions about an increased severity of the cosmic ray upset problem. In this paper we present a simple method of calculating cosmic ray upset rates. We compare the results of this method to results of an exact calculation and apply both methods to the prediction of upset rates as device feature sizes are scaled to submicron dimensions. The exact calculations are presented for several environmental predictions. We then discuss upset critical charge as a function of feature size. We consider upset rates versus scale parameter as a function of device size and critical charge. We conclude that upset rates do not increase catastrophically as devices scale down, but that the problem will be serious for all technologies. We also conclude that devices with small feature sizes will be susceptible to upsets by proton induced reactions, so that they will have serious problems in the proton radiation belt.
141 citations
IBM1
TL;DR: In this article, a single event-upset hardened CMOS data latch design is described and the hardness is achieved by virtue of the design; thus no fabrication process or design ground-rule development is required.
Abstract: A single-event-upset hardened CMOS data latch design is described. The hardness is achieved by virtue of the design; thus no fabrication process or design ground-rule development is required. Hardness is gained with comparatively little adverse impact on performance. Cyclotron tests have provided hardness verification. >
136 citations
"Upset hardened memory design for su..." refers methods in this paper
...These techniques are briefly illustrated in the upset-immune storage cell in Fig. 2 [ 8 ]....
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...Fig. 2. Upset-tolerant storage cell using a redundant slave latch [ 8 ]...
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01 Nov 1988
TL;DR: In this article, the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on micro-electronic ICs.
Abstract: Several technologies, including bulk and epi CMOS, CMOS/SOI-SOS (silicon-on-insulator-silicon-on-sapphire), CML (current-mode logic), ECL (emitter-coupled logic), analog bipolar (JI, single-poly DI, and SOI) and GaAs E/D (enhancement/depletion) heterojunction MESFET, are discussed. The discussion includes the direct effects of space radiation on microelectronic materials and devices, how these effects are evidenced in circuit and device design parameter variations, the particular effects of most significance to each functional class of circuit, specific techniques for hardening high-speed circuits, design examples for integrated systems, including operational amplifiers and A/D (analog/digital) converters, and the computer simulation of radiation effects on microelectronic ICs. >
113 citations
"Upset hardened memory design for su..." refers background in this paper
...Both latchup and total dose effects can be reduced to acceptable levels using some of the existing commercial CMOS technologies (e.g., bulk-epi processes) [ 2 ] ,[3]....
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TL;DR: In this paper, the authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique, which drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.
Abstract: The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition. >
103 citations