Using C-to-gates to program streaming image processing kernels efficiently on FPGAs
29 Sep 2009-pp 626-630
TL;DR: This paper applies algorithmic C-to-FPGA synthesis technology in a structured design approach and demonstrates its added value on two relevant vision processing kernels: optical flow and debayering.
Abstract: Effectively exploiting the variety of computational and storage resources available in common FPGA architectures for complex applications, such as the real-time implementation of vision algorithms, is often difficult in standard HDL design methodologies. Higher-level design tools can enable a design to more quickly explore a range of different architectures. In this paper we apply algorithmic C-to-FPGA synthesis technology in a structured design approach and demonstrate its added value on two relevant vision processing kernels: optical flow and debayering. The impact of the proposed approach on the design time, the FPGA resource consumption and the throughput is measured.
Citations
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TL;DR: AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx are used as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains.
Abstract: Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generations of commercial high-level synthesis (HLS) systems, we believe that the tipping point for transitioning to HLS msystem-on-chip design complexityethodology is happening now, especially for field-programmable gate array (FPGA) designs. The latest generation of HLS tools has made significant progress in providing wide language coverage and robust compilation technology, platform-based modeling, advancement in core HLS algorithms, and a domain-specific approach. In this paper, we use AutoESL's AutoPilot HLS tool coupled with domain-specific system-level implementation platforms developed by Xilinx as an example to demonstrate the effectiveness of state-of-art C-to-FPGA synthesis solutions targeting multiple application domains. Complex industrial designs targeting Xilinx FPGAs are also presented as case studies, including comparison of HLS solutions versus optimized manual designs. In particular, the experiment on a sphere decoder shows that the HLS solution can achieve an 11-31% reduction in FPGA resource usage with improved design productivity compared to hand-coded design.
728 citations
Cites methods from "Using C-to-gates to program streami..."
...The path-based scheduling algorithm in the Yorktown Silicon Compiler is useful to optimize performance with conditional branches [12]....
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...Industry efforts include Cathedral and its successors [27], Yorktown Silicon Compiler [11], and BSSC [93], among many others....
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05 Jun 2013
TL;DR: C code for a complex optical-flow algorithm is optimized for both a desktop PC and for an FPGA-based system, the Xilinx Zynq-7000, a device containing both a programmable fabric and two ARM cores.
Abstract: Recent developments in High-Level Synthesis (HLS) for FPGAs are making it possible to “run” C code on FPGAs thereby making modern programming environments available to FPGA developers. In this paper, C code for a complex optical-flow algorithm is optimized for both a desktop PC and for an FPGA-based system, the Xilinx Zynq-7000, a device containing both a programmable fabric and two ARM cores. The paper discusses how the code is optimized and restructured to execute effectively on the programmable fabric and the ARM cores. The resulting Zynq version of the C code is competitive with the desktop PC but only consumes 1/7th as much energy.
27 citations
Cites methods from "Using C-to-gates to program streami..."
...The Synfora PICO Extreme HLS tool was used to demonstrate the productivity of HLS for two machine vision algorithms including optical flow [9]....
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17 Apr 2016
TL;DR: The internal architecture of OpenSoC Fabric is described and its powerful list of configuration parameters are described and compared against pre-validated state-of-the-art simulators using both the generated C++ and Verilog models using FPGAs.
Abstract: As technology scaling continues, on-chip networks are expected to remain important in future many-core chips due to the increased parallelism and, therefore, communication. However, designing and evaluating large-scale on-chip networks is a nontrivial task given the poor scalability of software simulation for thousands of cores and the intense development effort to develop hardware RTL. In this paper, we describe OpenSoC Fabric. OpenSoC Fabric is a comprehensive on-chip network generator written in Chisel. Chisel generates both C++ and Verilog models from a single code base and has a development effort comparable to functional programming. We describe the internal architecture of OpenSoC Fabric and its powerful list of configuration parameters. We then compare OpenSoC Fabric against pre-validated state-of-the-art simulators using both the generated C++ and Verilog models using FPGAs.
24 citations
Cites background from "Using C-to-gates to program streami..."
...For instance, C to Gates [27] and SystemC [28] are well-known alternatives....
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01 Nov 2016
TL;DR: In this paper, image processing algorithms designed in Zynq SoC using the Vivado HLS tool are presented and compared with hand-coded designs, showing the reduction in time-to-market and the use of image processing libraries similar to OpenCV helps to reduce development time.
Abstract: In this paper, image processing algorithms designed in Zynq SoC using the Vivado HLS tool are presented and compared with hand-coded designs. In Vivado HLS, the designer has the opportunity to employ libraries similar to OpenCV, a library that is well-known and wide used by software designers. The algorithms are compared in terms of area resources in two conditions: using the libraries and not using the libraries. The case studies are Data Binning, a Step Row Filter and a Sobel Filter. These algorithms have been selected because they are very common in the field of image processing and they have high computational complexity. The main benefit of the Vivado HLS tool is the reduction in time-to-market. On the other hand, when a software designer hand-codes the design, the use of image processing libraries similar to OpenCV helps to reduce development time even further because software designers are familiar with them. However, using these kinds of libraries significantly increases the necessary FPGA resources.
23 citations
Cites background from "Using C-to-gates to program streami..."
...Moreover, we can find examples in different fields of application such as 3G/4G wireless systems [11], aerospace applications [12] and image processing [13] in real time environments....
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01 Dec 2013
TL;DR: This paper investigates matrix multiplication using a standard algorithm, Strassen algorithm, and a sparse algorithm to provide a comprehensive analysis of the capabilities and usability of the Xilinx Vivado HLS tool.
Abstract: One of the pitfalls of FPGA design is the relatively long implementation time when compared to alternative architectures, such as CPU, GPU or DSP. This time can be greatly reduced however by using tools that can generate hardware systems in the form of a hardware description language (HDL) from high-level languages such as C, C++, or Python. Such implementations can be optimized by applying special directives that focus the high-level synthesis (HLS) effort on particular objectives, such as performance, area, throughput, or power consumption. In this paper we examine the benefits of this approach by comparing the performance and design times of HLS generated systems versus custom systems for matrix multiplication. We investigate matrix multiplication using a standard algorithm, Strassen algorithm, and a sparse algorithm to provide a comprehensive analysis of the capabilities and usability of the Xilinx Vivado HLS tool. In our experience, a hardware-oriented electrical engineering student can achieve up to 61% of the performance of custom designs with 1/3 the effort, thus enabling faster hardware acceleration of many compute-bound algorithms.
20 citations
Cites methods from "Using C-to-gates to program streami..."
...utilized the Synfora PICO Extreme HLS tool to investigate the usefulness of HLS in lowering design time and increasing performance for vision processing kernels [7]....
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...The insertion of pipelining [2] is guided by characterization of the underlying FPGA architecture ....
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