Proceedings ArticleDOI
Using low-k oxide for reduction of leakage current in Double Gate Tunnel FET
Mahdi Vadizadeh,Morteza Fathipour +1 more
- pp 301-304
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TLDR
In this article, the double gate tunneling field effect transistors (DG-TFETs) were investigated to enhance I on /I off ratio in the Double Gate Tunneling Field Effect Transistor.Abstract:
In order to enhance I on /I off ratio in the Double Gate Tunneling Field Effect Transistor (DG-TFET), employing a double gate structure has been investigated. Furthermore by employing a low-k oxide for the gate near the drain side (Gate2) fringing field effects are suppressed. Hence, the leakage current is decreased. Also a work function engineering method has been employed for the gate near the source (Gate1) to further reduce the off state current.read more
Citations
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Proceedings Article
Scaling properties of the tunneling field effect transistor (TFET) : Device and circuit
Th. Nirschl,Henzler,J. Fischer,M. Fulde,A. Bargagli-Stoffi,M. Sterkel,J. Sedlmeir,Cory E. Weber,R. Heinrich,U. Schaper,J. Einfeld,R. Neubert,U. Feldmann,Knut Stahrenberg,E. Ruderer,Georg Georgakos,A. Huber,R. Kakoschke,Walter Hansch,Doris Schmitt-Landsiedel +19 more
TL;DR: In this paper, the scaling properties of TFETs were investigated using standard 130 nm, 90 nm, and 65 nm CMOS process flows. But the TFET dependence on the design parameters, i.e. channel width and length, is comparable to that of the standard MOSFET.
Patent
Tunnel field effect transistor with improved subthreshold swing
TL;DR: In this paper, the authors presented a tunnel field effect transistor (TFET) device comprising at least following segments: a highly doped drain region (3), a lowly doped up to undoped channel region (2) being in contact with said drain region, the channel region having a longitudinal direction, and the contact between the source region and the channel regions forming a source-channel interface (12), a gate dielectric (10) and a gate electrode (9) covering along the longitudinal direction at least part of the source and channel regions, said gate electrode(9
Journal ArticleDOI
Temperature effect on hetero structure junctionless tunnel FET
TL;DR: In this paper, the authors investigated the temperature effect on AlGaAs/Si based hetero-structure junctionless double gate tunnel field effect transistor (JT-FET).
Simulation of Double-Gate Silicon Tunnel FETs with a High-k Gate Dielectric
TL;DR: In this paper, a non-local band-to-band tunneling model is used to evaluate the performance of tunnel FETs, and the scaling limits of the threshold voltage at gate lengths on the order of 10-20 nm.
Journal ArticleDOI
Improving gate delay and I ON / I OFF in nanoscale heterostructure field effect diode (H-FED) by using heavy doped layers in the channel
TL;DR: In this paper, the effects of biaxial tensile strain on the electrical characteristics of the field effect diode (FED) in the nanometer regime were explored and a new structure, namely heterostructure FED (H-FED), was proposed, which does not turn off for channel lengths shorter than 75nm.
References
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Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Journal ArticleDOI
Complementary tunneling transistor for low power application
Peng-Fei Wang,K. Hilsenbeck,Th. Nirschl,M. Oswald,Ch. Stepper,M. Weis,Doris Schmitt-Landsiedel,Walter Hansch +7 more
TL;DR: In this paper, the complementary Si-based tunneling transistors are investigated in detail, and it is found that the band-to-band tunneling current is controlled by the gate-tosource voltage.
Journal ArticleDOI
Impact of the dimensionality on the performance of tunneling FETs: Bulk versus one-dimensional devices
TL;DR: In this article, the influence of dimensionality on the performance of tunneling field effect transistors is investigated with simulations and it is shown that in contrast to the 3D case, one-dimensional systems offer the possibility to combine a high on-state performance with steep inverse sub-threshold slopes.
Journal ArticleDOI
Vertical tunnel field-effect transistor
TL;DR: In this paper, a vertical field effect transistor (FET) with a vertical gate controlling the band-to-band tunneling width is presented, and the operation of the device is shown by means of both experimental results as well as two-dimensional computer simulations.
Journal ArticleDOI
A simulation approach to optimize the electrical parameters of a vertical tunnel FET
TL;DR: In this article, the electrical parameters of gated tunnel field effect transistor (FET) were optimized with a SiGe delta doped layer in the source region, which leads to an asymmetry in the n-and p-channel performance.