Variability-Aware Machine Learning Strategy for 3-D NAND Flash Memories
TL;DR: A variability-aware machine learning (ML) approach that predicts variations in the key electrical parameters of 3-D NAND Flash memories caused by various sources of variability and verified the accuracy, efficiency, and generality of artificial neural network (ANN) algorithm-based ML systems.
Abstract: This article proposes a variability-aware machine learning (ML) approach that predicts variations in the key electrical parameters of 3-D NAND Flash memories. For the first time, we have verified the accuracy, efficiency, and generality of the predictive impact factor effects of artificial neural network (ANN) algorithm-based ML systems. ANN-based ML algorithms can be very effective in multiple-input and multiple-output (MIMO) predictions. Therefore, changes in the key electrical characteristics of the device caused by various sources of variability are simultaneously and integrally predicted. This algorithm benchmarks 3-D stochastic TCAD simulation, showing a prediction error rate of less than 1%, as well as a calculation cost reduction of over 80%. In addition, the generality of the algorithm is confirmed by predicting the operating characteristics of the 3-D NAND Flash memory with various structural conditions as the number of layers increases.
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TL;DR: In this paper, an efficient and accurate DL approach with device simulation for gate-all-around silicon nanowire metal-oxide-semiconductor field effect transistors (MOSFETs) to predict electrical characteristics of device induced by work function fluctuation was presented.
Abstract: Device simulation has been explored and industrialized for over 40 years; however, it still requires huge computational cost. Therefore, it can be further advanced using deep learning (DL) algorithms. We for the first time report an efficient and accurate DL approach with device simulation for gate-all-around silicon nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) to predict electrical characteristics of device induced by work function fluctuation. By using three different DL models: artificial neural network (ANN), convolutional neural network (CNN), and long short term memory (LSTM), the variability of threshold voltage, on-current and off-current is predicted with respect to different metal-grain number and location of the low and high values of work function. The comparison is established among the ANN, CNN and the LSTM models and results depict that the CNN model outperforms in terms of the root mean squared error and the percentage error rate. The integration of device simulation with DL models exhibits the characteristic estimation of the explored device efficiently; and, the accurate prediction from the DL models can accelerate the process of device simulation. Notably, the DL approach is able to extract crucial electrical characteristics of a complicated device accurately with 2% error in a cost-effective manner computationally.
16 citations
TL;DR: Li et al. as discussed by the authors proposed an artificial neural network (ANN) to predict 7-parameters (i.e., off-state leakage current (Ioff), saturation drain current (Idsat), linear drain currents (Idlin), low drain currents, high drain currents and linear threshold voltage) which are usually used to evaluate the performance of FinFET.
Abstract: Line-edge-roughness (LER) is one of undesirable process-induced random variation sources. LER is mostly occurred in the process of photo-lithography and etching, and it provokes random variation in performance of transistors such as metal oxide semiconductor field effect transistor (MOSFET), fin-shaped field effect transistor (FinFET), and gate-all-around field effect transistor (GAAFET). LER was analyzed/characterized with technology computer-aided design (TCAD), but it is fundamentally very time consuming. To tackle this issue, machine learning (ML)-based method is proposed in this work. LER parameters (i.e., amplitude, and correlation length X, Y) are provided as inputs. Then, artificial neural network (ANN) predicts 7-parameters [i.e., off-state leakage current (Ioff), saturation drain current (Idsat), linear drain current (Idlin), low drain current (Idlo), high drain current (Idhi), saturation threshold voltage (Vtsat), and linear threshold voltage (Vtlin)] which are usually used to evaluate the performance of FinFET. First, how datasets for training process of ANN were generated is explained. Next, the evaluation method for probabilistic problem is introduced. Finally, the architecture of ANN, training process and our new proposition is presented. It turned out that the prediction results (i.e., non-Gaussian distribution of device performance metrics) obtained from the ANN were very similar to that from TCAD in the respect of both qualitative and quantitative comparison.
7 citations
TL;DR: In this paper, a program scheme to write the cells from the top, for instance the 170th layer, to the bottom, the 1st layer, (T-B scheme) in vertical NAND (VNAND) Flash Memory, is investigated to minimize Vt variation by reducing Z-interference.
Abstract: Minimizing the variation in threshold voltage (Vt) of programmed cells is required to the extreme level for realizing multi-level-cells; as many as even 5 bits per cell recently. In this work, a recent program scheme to write the cells from the top, for instance the 170th layer, to the bottom, the 1st layer, (T-B scheme) in vertical NAND (VNAND) Flash Memory, is investigated to minimize Vt variation by reducing Z-interference. With the aid of Technology Computer Aided Design (TCAD) the Z-Interference for T-B (84 mV) is found to be better than B-T (105 mV). Moreover, under scaled cell dimensions (e.g., Lg: 31→24 nm), the improvement becomes protruding (T-B: 126 mV and B-T: 162 mV), emphasizing the significance of the T-B program scheme for the next generation VNAND products with the higher bit density.
6 citations
References
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12 Jun 2007
TL;DR: Bit-Cost Scalable (BiCS) technology is proposed which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost.
Abstract: We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.
788 citations
"Variability-Aware Machine Learning ..." refers methods in this paper
...IN ORDER to increase device integration, the Flash memory industry has evolved from planar to 3-D-type NAND [2], [3]....
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TL;DR: Using 2 phase-change memory devices per synapse, a 3-layer perceptron network is trained on a subset of the MNIST database of handwritten digits using a backpropagation variant suitable for NVM+selector crossbar arrays, obtaining a training (generalization) accuracy of 82.2%.
Abstract: Using two phase-change memory devices per synapse, a three-layer perceptron network with 164 885 synapses is trained on a subset (5000 examples) of the MNIST database of handwritten digits using a backpropagation variant suitable for nonvolatile memory (NVM) + selector crossbar arrays, obtaining a training (generalization) accuracy of 82.2% (82.9%). Using a neural network simulator matched to the experimental demonstrator, extensive tolerancing is performed with respect to NVM variability, yield, and the stochasticity, linearity, and asymmetry of the NVM-conductance response. We show that a bidirectional NVM with a symmetric, linear conductance response of high dynamic range is capable of delivering the same high classification accuracies on this problem as a conventional, software-based implementation of this same network.
759 citations
"Variability-Aware Machine Learning ..." refers background in this paper
...optimization function is an optimization function that is known to be suitable for processing stochastic data, and that corrects the learning of the algorithm through iterative correction by the set error rate (η) [13], [16]....
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TL;DR: The state-of-the-art in the understanding of planar NAND Flash memory reliability is reviewed and how the recent move to three-dimensional (3D) devices has affected this field is discussed.
Abstract: We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.
81 citations
"Variability-Aware Machine Learning ..." refers background in this paper
...Although using such a 3-D structure and channel material is easy to integrate and costeffective, there are various limitations regarding the material and 3-D structure of the memory device [5]....
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10 May 2009
TL;DR: BiCS (Bit Cost Scalable) flash technology is focused as one of the most promising candidates for the future ultra high density storage devices.
Abstract: In this presentation, recent reports on three dimensional non-volatile memories are reviewed and their pros and cons are discussed. BiCS (Bit Cost Scalable) flash technology is focused as one of the most promising candidates for the future ultra high density storage devices.
35 citations
"Variability-Aware Machine Learning ..." refers methods in this paper
...IN ORDER to increase device integration, the Flash memory industry has evolved from planar to 3-D-type NAND [2], [3]....
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