Proceedings ArticleDOI
Variable Quality Factor JPEG Image Compression Using Dynamic Partial Reconfiguration and Microblaze
Juwairiyah Sarkhawas,Prasad D. Khandekar,Amruta A. Kulkarni +2 more
- pp 620-624
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TLDR
A system using the high performance, high capacity Virtex-4 FPGA for hardware acceleration of JPEG Image Compression Algorithm along with Microblaze and Dynamic Partial Reconfigurable (DPR) using Xilinx's PlanAhead tool to achieve on-the-fly multiple Quality Factors (Q) of the compressed images corresponding to different Image Qualities and sizes in varying application scenarios.Abstract:
As the possibilities and the technology offered by the reconfigurable devices is improving constantly, reconfigurable computing is becoming a research area of interest for many researchers. Till date FPGA is the core device for reconfigurable computing. On the fly partial reconfiguration (PR) is an attractive feature of FPGA, which has opened up new directions for researchers. This feature allows multiple functions to time-share the FPGA resources by exploiting reconfigurable area more efficiently. This paper designs a system using the high performance, high capacity Virtex-4 FPGA for hardware acceleration of JPEG Image Compression Algorithm along with Microblaze and Dynamic Partial Reconfigurable (DPR) using Xilinx's PlanAhead tool to achieve on-the-fly multiple Quality Factors (Q) of the compressed images corresponding to different Image Qualities and sizes in varying application scenarios.read more
Citations
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Journal ArticleDOI
Field-programmable gate arrays in a low power vision system
Ponnan Suresh,U. Saravanakumar,Celestine Iwendi,Senthilkumar Mohan,Gautam Srivastava,Gautam Srivastava +5 more
TL;DR: The implementation of the Dynamic Partial Reconfiguration technique to switch during runtime between two edge detection algorithms (FASTX and Sobel) in a computer vision algorithm has demonstrated the applicability of computer vision with low power consumption.
Dissertation
Exploring the implementation of JPEG compression on FPGA : a thesis presented in partial fulfilment of the requirements for the degree of Masters of Engineering in Electronics and Computer Systems Engineering at Massey University, Palmerston North, New Zealand
De Silva,Ann Malsha +1 more
TL;DR: The goal was to minimise the logic resources of the FPGA and the latency at each stage of compression and the resulting JPEG compressor has a latency of 8 rows of image readout plus 154 clock cycles.
Improved Subset Generation For The MU-Decoder
TL;DR: A chronology of key events leading to and including the 9/11 attacks is narrated by actor David Tennant.
Analyzing energy savings in an FPGA video processing system using dynamic partial reconfiguration
TL;DR: A chronology of key events and quotes from the 12-month investigation into the deaths of six British servicemen and women in the line of duty at the hands of Islamist extremists in Iraq and Syria is revealed.
Generation of Custom Run-Time Reconfigurable Hardware for Transparent Binary Acceleration
TL;DR: This work designed and evaluated a transparent binary acceleration approach, targeting Field Programmable Gate Array devices, which relies on instruction traces to automatically generate specialized accelerator instances, and which is capable of expediently generating accelerator-augmented embedded systems which achieve considerable performance increases whilst incurring a low resource cost, and without requiring manual hardware design.
References
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The JPEG2000 still image coding system: an overview
TL;DR: It is interesting to note that JPEG2000 is being designed to address the requirements of a diversity of applications, e.g. Internet, color facsimile, printing, scanning, digital photography, remote sensing, mobile applications, medical imagery, digital library and E-commerce.
Book
Design for Embedded Image Processing on FPGAs
TL;DR: Design for Embedded Image Processing on FPGAs is ideal for researchers and engineers in the vision or image processing industry, who are looking at smart sensors, machine vision, and robotic vision, as well as FPGA developers and application engineers.
BookDOI
Design for Embedded Image Processing on FPGAs: Bailey/Design for Embedded Image Processing on FPGAs
Proceedings ArticleDOI
FPGA based implementation of baseline JPEG decoder
TL;DR: FPGA based High speed, low complexity and low memory implementation of JPEG decoder is presented, allowing decompressing multiple image blocks simultaneously.