Variation-Tolerant In-Memory Digital Computations Using SRAM

TLDR: In this article, a variation-tolerant in-memory digital computation SRAM with on-chip built-in self-test (BIST) module for testing some of the core Boolean functions before placing the chip in the functional mode.

Abstract: The static random-access memory (SRAM) plays a vital role in the digital world as a storage device. Since there was no much innovation in processor and memory communication architecture, i.e., Von Neumann architecture which is the throughput bottleneck of the high-speed processor and low-speed memory. This bottleneck can be solved by attempting in-memory computation in SRAM and also as the scaling increases, the system on board became the system on chip where more functionality is packed on silicon chip by which the yield has become low and also the on-chip variation with multiple process voltage temperature (PVT) corners has become a major issue where the functional verification of memory has become a challenge to the designers. In this paper, we propose variation-tolerant in-memory digital computation SRAM with on-chip built-in self-test (BIST) module for testing some of the core Boolean functions before placing the chip in the functional mode. The investigated circuitry was validated with industry standard Cadence tools and the results confirm that the memory cell can store as well as compute the data.