Vertical GaN Split Gate Trench MOSFET with Improved High Frequency FOM
10 Dec 2020-
TL;DR: In this article, a new vertical GaN split gate trench MOSFET with a conventional trench gate MOS-FET for 600 V switching applications has been proposed, which exhibits 7 times lower HF-FOM (C rss ×R on ) and 3 times lower FOM (Q GD × R on ) without increase in the specific on-resistance, when compared to that of conventional MOS FET.
Abstract: Using TCAD Simulation, we present a systematic analysis and comparison of a new vertical GaN split gate trench MOSFET (SGT-MOSFET) with a conventional trench gate MOS-FET for 600 V switching applications We have calibrated our simulation models to match the experimental data as available in the literature We show that the SGT-MOSFET exhibits 7 times lower HF-FOM (C rss ×R on ) and 3 times lower HF-FOM (Q GD × R on ) without increase in the specific on-resistance, when compared to that of conventional MOSFET We, also have presented the main process steps required for the fabrication of the proposed device These improvements are important for reducing the conduction and switching losses, and making high frequency power conversion more efficient
Citations
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TL;DR: In this paper , a vertical GaN floating gate trench MOSFET was designed to obtain an enhanced high-frequency figure of merit (HF-FOM) than the conventional SGT- and TG-MOSFs.
Abstract: A vertical GaN floating gate trench MOSFET (FG-MOSFET) device structure has been optimized to obtain an enhanced high-frequency figure of merit (HF-FOM) than the conventional SGT- and TG-MOSFET. The floating gate (FG) electrode helps to reduce the surface electric field and binges in the middle of the drift layer. Using TCAD simulation, we demonstrate that with proper design of trench depth, drift doping, and field plate oxide thickness, the corresponding electric-field distribution for FG-MOSFET can be reduced to 2.3 MV cm−1. The proposed device has been designed for 600 V blocking voltage capability and with a specific on-resistance ( Ron ) as low as 0.73 mΩ cm2 due to the higher drift doping concentration. The HF-FOM ( QGD×Ron ) of FG-MOSFET shows a lower by two times and four times compared to SGT- and TG-MOSFET, due to FP oxide. Our results show that the FG-MOSFET device produces 15% and 47% reductions in the switching energy losses when compared with the similar current rated SGT- and TG-MOSFET devices, respectively.
3 citations
TL;DR: In this article , the authors proposed a vertical gallium nitride (GaN) parallel split gate trench MOSFET (PSGT) for power conversion applications, where two parallel gates and a field plate are introduced vertically on the sidewalls and connected, respectively, to the gate and source.
Abstract: This work proposes a vertical gallium nitride (GaN) parallel split gate trench MOSFET (PSGT-MOSFET) device architecture suitable for power conversion applications. Wherein two parallel gates, and a field plate are introduced vertically on the sidewalls and connected, respectively, to the gate and source. Technology computer-aided design (TCAD) simulator was used in the design process to achieve a specific on-resistance as low as 0.79 $\text{m}\Omega $ .cm2 for the device, which has the capacity of blocking voltages up to 600 V. The peak electric field of the PSGT-MOSFET could well be lowered to 2.95 MV/cm, which is about 17% lower than that of a conventional trench gate MOSFET (TG-MOSFET) near the trench corner with help of suitable design and optimization of trench depth, drift doping, and field plate thickness. The TCAD simulation shows that the higher drift doping on the device performance of PSGT-MOSFET produces $\sim 2\times $ lower switching losses when compared with a similarly rated conventional TG-MOSFET device.
TL;DR: In this article , the authors proposed a vertical gallium nitride (GaN) parallel split gate trench MOSFET (PSGT) for power conversion applications, where two parallel gates and a field plate are introduced vertically on the sidewalls and connected to the gate and source.
Abstract: This work proposes a vertical gallium nitride (GaN) parallel split gate trench MOSFET (PSGT-MOSFET) device architecture suitable for power conversion applications. Wherein two parallel gates, and a field plate are introduced vertically on the sidewalls and connected, respectively, to the gate and source. Technology computer-aided design (TCAD) simulator was used in the design process to achieve a specific on-resistance as low as 0.79 mΩ.cm 2 for the device, which has the capacity of blocking voltages up to 600 V. The peak electric field of the PSGT-MOSFET could well be lowered to 2.95 MV/cm, which is about 17% lower than that of a conventional trench gate MOSFET (TG-MOSFET) near the trench corner with help of suitable design and optimization of trench depth, drift doping, and field plate thickness. The TCAD simulation shows that the higher drift doping on the device performance of PSGT-MOSFET produces ~2× lower switching losses when compared with a similarly rated conventional TG-MOSFET device.
References
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TL;DR: In this article, the first GaN vertical transistor on silicon was demonstrated, based on a 6.7-thick n-p-n heterostructure grown on 6-inch silicon substrate by metal organic chemical-vapor deposition.
Abstract: We demonstrate the first GaN vertical transistor on silicon, based on a 6.7- $\mu \text{m}$ -thick n-p-n heterostructure grown on 6-inch silicon substrate by metal organic chemical-vapor deposition. The devices consist of trench-gate quasi-vertical metal–oxide–semiconductor field-effect transistors with a 4- $\mu \text{m}$ -thick drift layer, exhibiting enhancement-mode operation with a threshold voltage of 6.3V and an ON/OFF ratio of over 108. A high OFF-state breakdown voltage of 645 V along with a specific ON-resistance of $6.8~\textsf {m}\Omega \cdot \textsf {cm}^{{\textsf {2}}}$ were achieved thanks to the high-quality 4- $\mu \text{m}$ -thick GaN drift layer, presenting a relatively low defect density and very high electron mobility (720 cm $^{{\textsf {2}}}/\textsf {V}\cdot \textsf {s}$ ). This excellent performance represents a major step toward the realization of high-performance GaN vertical power transistors on low-cost silicon substrates.
74 citations
TL;DR: In this article, a robust fabrication method was developed based on a selective and local removal of the Si substrate as well as the resistive GaN buffer layers, followed by a conformal deposition of a 35- $\mu \text{m}$ -thick copper layer on the backside by electroplating, which provided excellent mechanical stability and electrical contact to the drain terminal.
Abstract: We report the first demonstration of fully vertical power MOSFETs on 6.6- $\mu \text{m}$ -thick GaN, grown on a 6-inch Si substrate by metal-organic chemical vapor deposition. A robust fabrication method was developed based on a selective and local removal of the Si substrate as well as the resistive GaN buffer layers, followed by a conformal deposition of a 35- $\mu \text{m}$ -thick copper layer on the backside by electroplating, which provides excellent mechanical stability and electrical contact to the drain terminal. The fabrication process of the gate trench was optimized, improving considerably the effective mobility at the p-GaN channel and the output current of the devices. High-performance fully vertical GaN-on-Si MOSFETs are presented, with a low specific ON-resistance ( ${R}_{\textsf {on,sp}}$ ) of 5 $\text{m}\Omega $ cm2 and a high OFF-state breakdown voltage of 520 V. Our results reveal a major step toward the realization of high-performance GaN vertical power devices on cost-effective Si substrates.
69 citations
TL;DR: The results show the potential of the OG-FET in power conversion applications.
Abstract: We present a large-area in-situ oxide, GaN interlayer-based vertical trench MOSFET (OG-FET) with a metal organic chemical vapor deposition regrown 10-nm unintentional-doped-GaN interlayer as the channel and 50-nm in-situ Al2O3 as the gate dielectric. The threshold voltage of the device on bulk GaN substrate was 1 V measured at $\text{I}_\mathrm {on}/\text{I}_\mathrm {off}= 10^{7}$ . The OG-FET with an area scaled to 0.2 mm2 demonstrated a breakdown voltage ( $\text{V}_\mathrm {BR}$ ) of 320 V and an on-state resistance ( $\text{R}_\mathrm {on}$ ) of $3.8~\Omega $ (specific on-state resistance: $\text{R}_\mathrm {on,sp}= 7.6\,\,\text{m}\Omega \,\,\cdot $ cm2). For the single unit cell OG-FET from the same sample, $\text{V}_\mathrm {BR}$ was as high as 700 V (measured at $\text{V}_\mathrm {GS}=-10$ V), corresponding to a breakdown electric field of 1.4 MV/cm and $\text{R}_\mathrm {on,sp}$ of 0.98 $\text{m}\Omega ~\cdot $ cm2. On our control sample, which was grown on sapphire substrate, a 1-A current was measured as well. These results show the potential of the OG-FET in power conversion applications.
56 citations
TL;DR: In this paper, a GaN vertical trench-MOSFET with a regrown channel was investigated, where the channel regrowth by MBE prevents repassivation of the p-type GaN body while promising higher channel mobility.
Abstract: GaN vertical trench-MOSFETs incorporating molecular beam epitaxy (MBE) regrown channel are developed and investigated. The channel regrowth by MBE prevents repassivation of the p-type GaN body while promising higher channel mobility. Two different designs of the lateral portion of the regrown channel are compared: without or with an n+-GaN buried layer. Without an n+ buried layer, a respectable 600-V breakdown voltage (BV) is measured in the absence of edge termination, indicating a decent critical field strength (>1.6 MV/cm) of the regrown channel. However, the ON-resistance is limited by the highly resistive lateral channel due to Mg incorporation. With an n+ buried layer, the limitation is removed. Excellent ON-current of 130 mA/mm and ON-resistivity of $6.4 ~\rm {m\Omega \cdot cm^{2}}$ are demonstrated. The BV is limited by high source–drain leakage current from the channel due to drain-induced barrier lowering (DIBL) effect. Device analysis together with TCAD simulations points out the major cause for the DIBL effect: the presence of interface charge beyond a critical value ( $\sim 6\times 10^{12}\,\,\rm {cm^{-2}}$ ) at the regrowth interface on etched sidewalls. This paper provides valuable insights into the design of GaN vertical trench-MOSFET with a regrown channel, where simultaneous achievement of low ON-resistivity and high BV is expected in devices with reduced interface charge density and improved channel design to eliminate DIBL.
44 citations
TL;DR: In this article, the leakage current of a pn diode on a GaN substrate isolated by a mesa structure at a reverse bias was studied on a surface of the mesa sidewall across the pn junction.
Abstract: In this paper, we studied on a leakage current of a pn diode on a GaN substrate isolated by a mesa structure at a reverse bias. The leakage current flowed at a surface of the mesa sidewall across the pn junction. Results of scanning capacitance microscopy and scanning spread resistance microscopy indicated that the surface of the mesa sidewall in the p type region changed to a depleted or a n--layer. Results of auger electron spectroscopy indicated that a concentration of nitrogen decreased near the surface of the mesa sidewall. From these results, we estimated the leakage current was caused by a change of the p type region at the surface of the mesa sidewall to the depleted or n--layer by inductively coupled plasma dry etching, which was used to form the mesa structure. (© 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)
24 citations