Journal ArticleDOI
Vertical Si-Nanowire $n$ -Type Tunneling FETs With Low Subthreshold Swing ( $\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature
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TLDR
In this article, a Si nanowire based tunneling field effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure has been presented.Abstract:
This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high Ion/Ioff ratio (105), as well as low Drain-Induced Barrier Lowering of 70 mV/V.read more
Citations
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Journal ArticleDOI
Electronics based on two-dimensional materials
Gianluca Fiori,Francesco Bonaccorso,Giuseppe Iannaccone,Tomas Palacios,Daniel Neumaier,Alan Seabaugh,Sanjay K. Banerjee,Luigi Colombo +7 more
TL;DR: A review of electronic devices based on two-dimensional materials, outlining their potential as a technological option beyond scaled complementary metal-oxide-semiconductor switches and the performance limits and advantages, when exploited for both digital and analog applications.
Journal ArticleDOI
Tunnel Field-Effect Transistors: State-of-the-Art
Hao Lu,Alan Seabaugh +1 more
TL;DR: In this paper, the development of tunnel field-effect transistors (TFETs) is reviewed by comparing experimental results and theoretical predictions against 16-nm FinFET CMOS technology.
Journal ArticleDOI
2D-2D tunneling field-effect transistors using WSe2/SnSe2 heterostructures
Tania Roy,Tania Roy,Mahmut Tosun,Mahmut Tosun,Mark Hettick,Mark Hettick,Geun Ho Ahn,Geun Ho Ahn,Chenming Hu,Ali Javey,Ali Javey +10 more
TL;DR: In this article, the authors demonstrate 2D-2D tunneling in a WSe2/SnSe2 van der Waals vertical heterojunction device, where WSe 2 is used as the gate controlled p-layer and SnSe2 is the degenerately n-type layer.
Journal ArticleDOI
Proposal for tunnel-field-effect-transistor as ultra-sensitive and label-free biosensors
Deblina Sarkar,Kaustav Banerjee +1 more
TL;DR: In this paper, a tunnel field effect transistor (TFET) based biosensor is proposed, and it is shown that they can surpass by several orders, the performance of those based on conventional FET and hence, can potentially revolutionize the biosensing applications.
Journal ArticleDOI
Nanowire Electronics: From Nanoscale to Macroscale
TL;DR: A comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics, including a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics.
References
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Journal ArticleDOI
Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec
TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Journal ArticleDOI
Double-Gate Tunnel FET With High- $\kappa$ Gate Dielectric
Kathy Boucart,Adrian M. Ionescu +1 more
TL;DR: In this article, a double-gate tunnel field effect transistor (DG tunnel FET) with a high-kappa gate dielectric was proposed and validated using realistic design parameters, showing an on-current as high as 0.23 mA for a gate voltage of 1.8 V, an off-current of less than 1 fA (neglecting gate leakage), an improved average sub-threshold swing of 57 mV/dec, and a minimum point slope of 11 mV /dec.
Proceedings ArticleDOI
Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope
TL;DR: In this paper, a Double-Gate, Strained-Ge, Heterostructure Tunneling FET (TFET) exhibiting very high drive currents and SS < 60 mV/dec was experimentally demonstrated.
Journal ArticleDOI
Scaling the vertical tunnel FET with tunnel bandgap modulation and gate workfunction engineering
TL;DR: It is shown here that the tunnel FET performance is nearly independent of channel length scaling L and with /spl delta/p/sup +/ SiGe layer, scaling t/sub ox/ is not critical to Tunnel FET scaling.
Journal ArticleDOI
Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits
Yasin Khatami,Kaustav Banerjee +1 more
TL;DR: In this paper, the authors proposed n-and p-type tunnel field effect transistors (T-FETs) based on heterostructure Si/intrinsic-SiGe channel layer, which exhibit very small subthreshold swings, as well as low threshold voltages.