Vertically integrated silicon-germanium nanowire field-effect transistor
TL;DR: In this article, the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field effect transistors (FETs) was demonstrated and a threshold voltage close to 3.9 V was reported.
Abstract: We demonstrate in this paper the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field-effect transistors (FETs). We report a threshold voltage close to 3.9 V, an ION/IOFF ratio of 104. The subthreshold slope was estimated to be around 0.9 V/decade and explained by a high traps density at the nanowire core/oxide shell interface with an estimated density of interface traps Dit ∼ 1.2 × 1013 cm−2 eV−1. Comparisons are made with both vertical Si and horizontal SiGe FETs performances.
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TL;DR: Basic Principles to Advanced Applications Michele Amato,*, Maurizia Palummo,*,‡ Riccardo Rurali,* and Stefano Ossicini.
Abstract: Basic Principles to Advanced Applications Michele Amato,*,† Maurizia Palummo,*,‡ Riccardo Rurali,* and Stefano Ossicini* †Institut d’Electronique Fondamentale, UMR8622, CNRS, Universite ́ Paris-Sud, 91405 Orsay, France ‡European Theoretical Spectroscopy Facility (ETSF), Dipartimento di Fisica, Universita ̀ di Roma, “Tor Vergata”, Via della Ricerca Scientifica 1, 00133 Roma, Italy Institut de Cieǹcia de Materials de Barcelona (ICMAB−CSIC), Campus de Bellaterra, 08193 Bellaterra, Barcelona, Spain “Centro S”, CNR-Istituto di Nanoscienze, Via Campi 213/A, 41125 Modena, Italy Dipartimento di Scienze e Metodi dell’Ingegneria, Centro Interdipartimentale En&Tech, Universita ̀ di Modena e Reggio Emilia, Via Amendola 2 Pad. Morselli, I-42100 Reggio Emilia, Italy
144 citations
01 Jan 2012
TL;DR: In this article, a strain-gated piezotronic transistors were fabricated using vertically aligned ZnO nanowires (NWs), which were grown on GaN/sapphire substrates using a vapor-liquidsolid process.
Abstract: Strain-gated piezotronic transistors have been fabricated using vertically aligned ZnO nanowires (NWs), which were grownon GaN/sapphire substrates using a vaporliquidsolid process. The gate electrode of the transistor is replaced by the internal crystal potential generated by strain, and the control over the transported current is at the interface between the nanowire and the top or bottom electrode. The currentvoltage characteristics of the devices were studied using conductive atomic force microscopy, and the results show that the current flowing through the ZnO NWs can be tuned/gated by the mechanical force applied to the NWs. This phenomenon was attributed to the piezoelectric tuning of the Schottky barrier at the AuZnO junction, known as the piezotronic effect. Our study demonstrates the possibility of using Au droplet capped ZnO NWs as a transistor array for mapping local strain. More importantly, our design gives the possibility of fabricating an array of transistors using individual vertical nanowires that can be controlled independently by applying mechanical force/pressure over the top. Such a structure is likely to have important applications in high- resolution mapping of strain/force/pressure.
89 citations
TL;DR: These studies show that junctionless transistors based on vertical Ge/Si core/shell nanowires can be fabricated in a controlled fashion with excellent performance and may be used in future hybrid, high-performance circuits where bottom-up grown nanowire devices with different functionalities can be directly integrated with an existing Si platform.
Abstract: Vertical junctionless transistors with a gate-all-around (GAA) structure based on Ge/Si core/shell nanowires epitaxially grown and integrated on a ⟨111⟩ Si substrate were fabricated and analyzed. Because of efficient gate coupling in the nanowire-GAA transistor structure and the high density one-dimensional hole gas formed in the Ge nanowire core, excellent P-type transistor behaviors with Ion of 750 μA/μm were obtained at a moderate gate length of 544 nm with minimal short-channel effects. The experimental data can be quantitatively modeled by a GAA junctionless transistor model with few fitting parameters, suggesting the nanowire transistors can be fabricated reliably without introducing additional factors that can degrade device performance. Devices with different gate lengths were readily obtained by tuning the thickness of an etching mask film. Analysis of the histogram of different devices yielded a single dominate peak in device parameter distribution, indicating excellent uniformity and high confi...
39 citations
TL;DR: In the nonlinearly driven cantilever, the adsorption and desorption-induced frequency shifts were enhanced by over a factor of three compared to resonant sensing with the same mode in the linear regime, demonstrating a route towards gas detectors that exploit nonlinearity to enhance the responsivity.
Abstract: Cantilevers play an important role as linear transducers in nanoscience, with nanomechanical detection of mass and stress as a clear example. We performed gas sensing experiments with a standard functionalized cantilever driven strongly into the regime of nonlinear oscillations. We compared the cantilever response to the selective adsorption of ethanol vapour in the nonlinear regime, to the ones obtained in the conventional linear static and dynamic sensing modes. In the nonlinearly driven cantilever, the adsorption and desorption-induced frequency shifts were enhanced by over a factor of three compared to resonant sensing with the same mode in the linear regime. This demonstrates a route towards gas detectors that exploit nonlinearity to enhance the responsivity, which can be implemented with standard cantilever devices.
33 citations
TL;DR: It is shown that vertical arrays of NiO-NPs are potential candidates for nanoscale devices because they have a great impact on the local current transport mechanism due to its nanostructure morphology.
Abstract: The present work focuses on a qualitative analysis of localised I–V characteristics based on the nanostructure morphology of highly dense arrays of p-type NiO nano-pillars (NiO-NPs). Vertically aligned NiO-NPs have been grown on different substrates by using a glancing angle deposition (GLAD) technique. The preferred orientation of as grown NiO-NPs was controlled by the deposition pressure. The NiO-NPs displayed a polar surface with a microscopic dipole moment along the (111) plane (Tasker's type III). Consequently, the crystal plane dependent surface electron accumulation layer and the lattice disorder at the grain boundary interface showed a non-uniform current distribution throughout the sample surface, demonstrated by a conducting AFM technique (c-AFM). The variation in I–V for different points in a single current distribution grain (CD-grain) has been attributed to the variation of Schottky barrier height (SBH) at the metal–semiconductor (M–S) interface. Furthermore, we observed that the strain produced during the NiO-NPs growth can modulate the SBH. Inbound strain acts as an external field to influence the local electric field at the M–S interface causing a variation in SBH with the NPs orientation. This paper shows that vertical arrays of NiO-NPs are potential candidates for nanoscale devices because they have a great impact on the local current transport mechanism due to its nanostructure morphology.
24 citations
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14,205 citations
TL;DR: In this article, a broad array of nanowire building blocks available to researchers and discuss a range of electronic and optoelectronic nanodevices, as well as integrated device arrays, that could enable diverse and exciting applications in the future.
1,352 citations
TL;DR: In this paper, the authors demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field effect transistors without the need for postgrowth nanowires assembly processes.
Abstract: Silicon nanowires have received considerable attention as transistor components because they represent a facile route toward sub-100-nm single-crystalline Si features. Herein we demonstrate the direct vertical integration of Si nanowire arrays into surrounding gate field effect transistors without the need for postgrowth nanowire assembly processes. The device fabrication allows Si nanowire channel diameters to be readily reduced to the 5-nm regime. These first-generation vertically integrated nanowire field effect transistors (VINFETs) exhibit electronic properties that are comparable to other horizontal nanowire field effect transistors (FETs) and may, with further optimization, compete with advanced solid-state nanoelectronic devices.
781 citations
TL;DR: In this paper, the authors demonstrate a bottom-up integration of a semiconductor 1D nanowire, using zinc oxide (ZnO) as an example, to obtain a vertical surround-gate field effect transistor (VSG-FET).
Abstract: Harnessing the potential of single crystal inorganic nanowires for practical advanced nanoscale applications requires not only reproducible synthesis of highly regular one-dimensional (1D) nanowire arrays directly on device platforms but also elegant device integration which retains structural integrity of the nanowires while significantly reducing or eliminating complex critical processing steps. Here we demonstrate a unique, direct, and bottom-up integration of a semiconductor 1D nanowire, using zinc oxide (ZnO) as an example, to obtain a vertical surround-gate field-effect transistor (VSG-FET). The vertical device structure and bottom-up integration reduce process complexity, compared to conventional top-down approaches. More significantly, scaling of the vertical channel length is lithographically independent and decoupled from the device packing density. A bottom electrical contact to the nanowire is uniquely provided by a heavily doped underlying lattice-match substrate. Based on the nanowire-integrated platform, both n- and p-channel VSG-FETs are fabricated. The vertical device architecture has the potential for use in tera-level ultrahigh-density nanoscale memory and logic devices.
668 citations