![Figure 13. Minimum Extraction Unit correction factor σ in (6) is applied before the final addition in (5) and λnewk [c] are sent to the output buffer.](/figures/figure-13-minimum-extraction-unit-correction-factor-s-in-6-1ev8ko1t.webp)
10 August 2022
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VLSI implementation of a multi-mode turbo/LDPC decoder architecture / Condo, Carlo; Martina, Maurizio; Masera,
Guido. - In: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS. - ISSN 1549-8328. -
STAMPA. - 60:6(2013), pp. 1441-1454. [10.1109/TCSI.2012.2221216]
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VLSI implementation of a multi-mode turbo/LDPC decoder architecture
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1
VLSI implementation of a multi-mode turbo/LDPC
decoder architecture
Carlo Condo, Maurizio Martina, Member IEEE, Guido Masera, Senior Member IEEE
Dipartimento di Elettronica e Telecomunicazioni, Politecnico di Torino, Italy
Abstract—Flexible and reconfigurable architectures have
gained wide popularity in the communications field. In particular,
reconfigurable architectures for the physical layer are an attrac-
tive solution not only to switch among different coding modes
but also to achieve interoperability. This work concentrates on
the design of a reconfigurable architecture for both turbo and
LDPC codes decoding. The novel contributions of this paper
are: i) tackling the reconfiguration issue introducing a formal
and systematic treatment that, to the best of our knowledge, was
not previously addressed; ii) proposing a reconfigurable NoC-
based turbo/LDPC decoder architecture and showing that wide
flexibility can be achieved with a small complexity overhead.
Obtained results show that dynamic switching between most of
considered communication standards is possible without pausing
the decoding activity. Moreover, post-layout results show that
tailoring the proposed architecture to the WiMAX standard leads
to an area occupation of 2.75 mm
2
and a power consumption of
101.5 mW in the worst case.
Index Terms—VLSI, LDPC/Turbo Codes Decoder, NoC, Flex-
ibility, Wireless communications
I. INTRODUCTION
In the last years several efforts were spent to develop
systems able to give ubiquitous access to telecommunication
networks. These efforts were spent mainly in three directions:
i) improving the transmission rate and reliability; ii) develop-
ing bandwidth efficient technologies; iii) designing low cost
receivers. The most relevant results produced by such a vivid
research were included in the last standards for both wireless
and wired communications [1]–[7]. Besides, several standards
provide multiple modes and functionalities. However, sharing
common features is a challenging task to achieve flexibility
and interoperability.
Several recent works, including [8], have shown that flex-
ibility is an important property in the implementation of
communication systems. Some works investigated this di-
rection facing the challenge of implementing flexible archi-
tectures for the decoding of channel codes. In particular,
flexible turbo/Low-Density-Parity-Check (LDPC) decoder ar-
chitectures have been proposed not only to support differ-
ent coding modes within a specific standard but also to
enable interoperability among different standards. In [9]–
[11] flexibility is achieved through the design of Processing
Elements (PEs) based on Application-Specific-Instruction-set-
Processor (ASIP) architectures, whereas in [12]–[14] PEs rely
on Application-Specific-Integrated-Circuit (ASIC) solutions.
In both approaches, flexible and efficient interconnection struc-
tures are required to connect PEs to each other.
Unfortunately, the communication patterns of turbo and
LDPC codes suffer from collisions, namely two or more PEs
require concurrent access to the same memory resource. To
break the collision a Network-on-Chip (NoC) like approach
was proposed in [15] for turbo codes. This idea has been
further developed in other works. In particular, in [16] the NoC
approach is used as a viable solution to implement flexible and
high throughput interconnection structures for turbo/LDPC
decoders.
An intra-IP NoC [17] is an application specific NoC [18]
where the interconnection structure is tailored to the char-
acteristics of the Intellectual Property (IP). The use of an
intra-IP NoC as the interconnection framework for both turbo
and LDPC code decoders has been demonstrated in several
works [16], [19]–[21]. This choice enables larger flexibility
with respect to other interconnection schemes [16], [22], [23],
but introduces penalties in terms of additional occupied area
and latency in the communication among PEs.
Stemming from the work presented in [14], [19], [20],
where an ASIC implementation of an NoC-based turbo/LDPC
decoder architecture is proposed, this paper aims to further
investigate and optimize it. In particular, this work features
the following novel contributions: i) management of dynamic
reconfiguration to switch between a code to another one
without pausing the decoding, ii) description of a new PE
architecture with an improved shared memory solution which
provides relevant saving of occupied area for min-sum de-
coding algorithm, iii) evaluation of a wide set of standards for
both wireless and wired applications: IEEE 802.16e (WiMAX)
[5], IEEE 802.11n (WiFi) [6], China Mulitimedia Mobile
Broadcasting (CMMB) [3], Digital Terrestrial Multimedia
Broadcast (DTMB) [4], HomePlug AV (HPAV) [2], 3GPP
Long Term Evolution (LTE) [7], Digital Video Broadcasting
- Return Channel via Satellite (DVB-RCS) [1], iv) complete
VLSI implementation of the decoder up to layout level and
accurate evaluation of dissipated power.
It is worth noting that, to the best of our knowledge, this is
the first work addressing dynamic reconfiguration of flexible
channel decoders with an analytical approach, and showing
the actual impact of reconfiguration on both performance and
complexity. The paper is structured as follows. In Section
II decoding algorithms are briefly discussed, whereas section
III deals with the basics of NoC-based turbo/LDPC decoder
architectures and summarizes the main results this work starts
from. The decoder reconfiguration techniques are detailed in
Section IV and V, while Section VI deals with the descrip-
tion of LDPC and turbo decoding cores, along with their
respective memory organization. In Section VII evaluations of
the architecture performance on various existing standards are
provided. Implementation results are portrayed and discussed
in Section VIII, and conclusions are drawn in section IX.
II. DECODING ALGORITHMS
Turbo and LDPC decoding algorithms are characterized
by strong resemblances: they are iterative, work on graph-
based representations, are routinely implemented in logarith-
mic form, process data expressed as Logarithmic-Likelihood-
Ratios (LLRs) and require high level of both processing and
storage parallelism. Both algorithms receive intrinsic informa-
tion from the channel and produce extrinsic information that is
exchanged across iterations to obtain the a priori information
of uncoded bits, in the case of binary codes, or symbols, in
the case of non binary codes. Moreover, their arithmetical
functions are so similar that joint or derived algorithms for
both LDPC and turbo decoding exist [24]. In the following
for both codes we will refer to K, N and r = K/N as the
number of uncoded bits, the number of coded bits and the
code rate respectively.
A. LDPC codes decoding algorithm
Every LDPC code is completely described by its M × N
parity check matrix H (M = N − K) which is very sparse
[25]. Each valid LDPC codeword x satisfies H · x
0
= 0,
where (·)
0
is the transposition operator. The decoding of LDPC
codes stems from the Tanner graph representation of H where
two sets of nodes are identified: Variable Nodes (VNs) and
Check Nodes (CNs). VNs are associated to the N bits of the
codeword, whereas CNs correspond to the M parity-check
constraints. The most common algorithm to decode LDPC
codes is the Belief Propagation (BP) algorithm. There are two
main scheduling schemes for the BP: two-phase scheduling
and layered scheduling [26]. The latter nearly doubles the
converge speed as compared to two-phase scheduling. In a
layered decoder, parity-check constraints are grouped in layers
each of which is associated to a component code. Then, layers
are decoded in sequence by propagating extrinsic information
from one layer to the following one [26]. This process is
iterated up to the desired level of reliability.
Let λ[c] represent the LLR of symbol c and, for column k
in H, bit LLR λ
k
[c] is initialized to the corresponding received
soft value. Then, for all parity constraints l in a given layer,
the following operations are executed:
Q
lk
[c] = λ
old
k
[c] − R
old
lk
(1)
A
lk
=
X
n∈N(l),n6=k
Ψ(Q
ln
[c]) (2)
δ
lk
=
Y
n∈N(l),n6=k
sgn(Q
ln
[c]) (3)
R
new
lk
= −δ
lk
· Ψ
−1
(A
lk
) (4)
λ
new
k
[c] = Q
lk
[c] + R
new
lk
(5)
λ
old
k
[c] is the extrinsic information received from the previous
layer and updated in (5) to be propagated to the succeed-
ing layer. Term R
old
lk
, pertaining to element (l,k) of H and
initialized to 0, is used to compute (1); the same amount is
then updated in (4), R
new
lk
, and stored to be used again in the
following iteration. In (2) and (3) N(l) is the set of all bit
indexes that are connected to parity constraint l.
According to [27], the Ψ(·) function in (2) and (4) can be
simplified with a limited BER performance loss as
R
new
lk
≈ −δ
0
lk
· min
n∈N(l),n6=k
{|Q
nk
|} , (6)
usually referred to as normalized-min-sum approximation,
where δ
0
lk
= σ · δ
lk
and σ ≤ 1.
B. Turbo codes decoding algorithm
Turbo codes are obtained as the parallel concatenation of
two constituent Convolutional Code (CC) encoders connected
by the means of an interleaver (Π). Thus, the decoder is
made of two constituent decoders, referred to as Soft-In-Soft-
Out (SISO) or Maximum-A-Posteriori (MAP) decoders [28]
connected in an iterative loop by the means of the interleaver
Π and the de-interleaver Π
−1
. Each constituent decoder per-
forms the so called BCJR algorithm [29] that starting from
the intrinsic and a priori information produces the extrinsic
information. Let k be a step in the trellis representation of the
constituent CC, and u an uncoded symbol. Each constituent
decoder computes λ
k
[u] = σ · (λ
apo
k
[u] − λ
apr
k
[u] − λ
k
[c
u
])
where σ ≤ 1 [30], λ
apo
k
[u] is the a-posteriori information,
λ
apr
k
[u] is the a priori information and λ
k
[c
u
] is the systematic
component of the intrinsic information. According to [29] a-
posteriori information is computed as
λ
apo
k
[u] =
∗
max
e:u(e)=u
{b(e)} −
∗
max
e:u(e)=˜u
{b(e)} (7)
where ˜u ∈ U is an uncoded symbol taken as a reference
(usually ˜u = 0) and u ∈ U \ {˜u} with U the set of uncoded
symbols; e is a trellis transition and u(e) is the corresponding
uncoded symbol. Several exact and approximated expressions
are available for the
∗
max{x
i
} function [31]: for example, it
can be implemented as max{x
i
} followed by a correction
term, often stored in a small Look-Up-Table (LUT). The
correction term, usually adopted when decoding binary codes
(Log-MAP), can be omitted with minor Bit-Error-Rate (BER)
performance degradation (Max-Log-MAP). The term b(e) in
(7) is defined as:
b(e) = α
k−1
[s
S
(e)] + γ
k
[e] + β
k
[s
E
(e)] (8)
α
k
[s] =
∗
max
e:s
E
(e)=s
α
k−1
[s
S
(e)] + γ
k
[e]
(9)
β
k
[s] =
∗
max
e:s
S
(e)=s
β
k+1
[s
E
(e)] + γ
k
[e]
(10)
γ
k
[e] = λ
apr
k
[u(e)] + λ
k
[c(e)] (11)
where s
S
(e) and s
E
(e) are the starting and the ending states
of e, α
k
[s
S
(e)] and β
k
[s
E
(e)] are the forward and backward
metrics associated to s
S
(e) and s
E
(e) respectively. The term
λ
k
[c(e)] represents the intrinsic information received from the
Routing
algorithm
crossbar
conf.
Memory
Location
load
read enable
MEM iPE i
output
bus
RE i
λ
0
i,j
λ
i,j
t
0
i,j
input
Reconfiguration
Figure 1. Node structure
channel. For further details on the decoding algorithm the
reader can refer to [32].
In a parallel decoder, the decoding operations summarized
in previous paragraphs are partitioned among P PEs. When
configured in turbo code mode, these PEs operate as con-
current SISOs. On the other hand, they execute (1) to (5)
in parallel for P slices of parity check constraints when
configured in LDPC code mode. In both cases, messages
are exchanged among PEs to propagate λ
k
[u] and λ
new
k
[c]
amounts in accordance with the code structure. In the follow-
ing, we indicate the j-th message received and generated by
PE i as λ
0
i,j
and λ
i,j
respectively.
III. NOC-BASED DECODER
The goal of this work is to design a highly flexible LDPC
and turbo decoder, able to support a very wide set of different
communication standards. The proposed multi-mode/multi-
standard decoder architecture relies on an NoC-based struc-
ture, where each node contains a PE and a routing element
(RE). Each PE implements the BCJR and layered normalized
min-sum algorithms. On the other hand, REs are devoted to
deliver λ
i,j
values to the correct destination.
The node architecture employed in this work for node i is
represented in Fig. 1. Each RE is constituted by a 4×4 crossbar
switch with 4 input FIFOs and 4 output registers. The routing
algorithm is the one proposed in [19] as Single-Shortest-
Path-FIFO-Length (SSP-FL). SSP-FL relies on a distributed
table-based routing algorithm where each table contains the
information for shortest path routing. The routing information
is precalculated by running off-line the Floyd-Warshall algo-
rithm. Moreover, in SSP-FL shortest path routing is coupled
with an input serving policy based on the current status to
the FIFOs, namely in case two messages must be routed to
the same output port, priority is given to the message coming
from the longer FIFO. It is worth noting that the destination
of each λ
i,j
is imposed by the interleaver and the H matrix
respectively. As a consequence, the routing is deterministic.
The PE includes both LDPC and turbo decoding cores:
their architectures are structured to be as independent as
possible of the supported codes. The LDPC decoding core
is completely serial and able to decode any LDPC code,
provided that enough memory is available. The SISO core
for turbo decoding is tailored around 8-state turbo codes,
and no other constraints are present: the two cores share the
memories where the incoming data λ
0
i,j
are stored and the
location memory containing the pre-computed t
0
i,j
values, i.e.
the memory addresses to store λ
0
i,j
. Also the interconnection
structure depends only on the location memory size, that sets
an upper bound to the number of messages each PE can
handle.
The decoding task is divided uniformly among the different
nodes. The process is straightforward in turbo mode, with
each node being assigned a portion of the trellis that is
processed in a sliding-window fashion [33], [34]. Extrinsic
and window-initialization information are carried through the
network according to the code interleaving and deinterleaving
rules [19]. On the contrary, in LDPC mode the partitioning
of the decoding task on the PEs is obtained as follows.
Using a proprietary tool based on the METIS graph coloring
library [35], the H matrix is partitioned on the chosen network
topology. At this point the destination of every message
coming out of each decoding core is known. Thus, in both
turbo and LDPC modes each outgoing message is made of a
payload λ
i,j
and a header containing the destination node.
Performance of meshes, toroidal meshes, spidergon, hon-
eycomb, De Bruijn and Kautz graphs were compared, along
with a number of other design choices, as routing algorithm
and collision management policies. This analysis shows that
the Kautz topology yields the best results in terms of area
occupation and obtainable throughput. In particular, in [14] a
22-nodes Kautz NoC was used to fully support IEEE 802.16e
standard, each node being connected to a decoding PE and to
three other nodes via a 4-way router.
IV. DECODER RECONFIGURATION
Flexible decoders available in the literature [9]–[13], [16],
[17], [19], [20], though supporting a wide range of codes,
do not address the reconfiguration issue. Change of decoding
mode, standard or code parameters requires not only hardware
support, but also memory initialization and specific controls:
since in many standards a code switch can be issued as early
as one data frame ahead [5], a time efficient reconfiguration
technique must be developed.
For the proposed decoder the reconfiguration task consists
of i) rewriting the location memory containing t
0
i,j
values; ii)
reloading the CN degree (deg) parameters and the window
size in the control unit of LDPC decoding cores and SISOs
respectively. In the following, the whole set of storage loca-
tions to be updated at reconfiguration time will be indicated as
“reconfiguration memory”. When possible, the decoder must
be reconfigured while the decoding process is still running on
the previous data frame. This means that the reconfiguration
data can be distributed by means of the NoC interconnections
only at the cost of severe performance penalties. Consequently,
we suppose that the reconfiguration data are moved directly
to the PEs via a set of N
b
dedicated buses, each one linked
to
P
N
b
PEs.
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
11111
11111
11111
11111
11111
11111
11111
11111
11111
11111
11111
00000
00000
00000
00000
00000
00000
00000
11111
11111
11111
11111
11111
11111
11111
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
000000
111111
111111
111111
111111
111111
111111
111111
111111
111111
111111
111111
000000
000000
000000
000000
000000
111111
111111
111111
111111
111111
000000
000000
000000
111111
111111
111111
00
00
00
00
11
11
11
11
RP
ECC
SCC
(c)
SCC
ECC
SFC
WP
RP
EFC
(b)
ECC
RP
SCC
(a)
Locations occupied by C
1
Free locations Locations uploaded with C
2
Figure 2. Memory reconfiguration process: (a) Decoding of C
1
; (b) Upload
of reconfiguration data required for C
2
(phases Φ
1
to Φ
3
and Φ
5
); (c) First
iteration of C
2
and concurrent upload of reconfiguration data (Φ
4
)
In the following we estimate reconfiguration occurrence
assuming mobile receivers moving at different speeds and
the carrier frequency f
c
= 2.4 GHz. This frequency is
included in most standards’ operation range, and used in a
variety of applications. In this scenario the communication
channel is affected by fading phenomena, namely slow fading,
whose effects have very long time constants, and fast fading.
Fast fading can be modeled assuming a change of channel
conditions every time the receiver is moved by a distance
similar to the wavelength λ of the carrier. Being λ = 0.125
m, at a speed v = 70 km/h the channel changes with a
frequency f
chng
= 155 Hz (WiMAX, WiFi, 3GPP-LTE),
whereas, at v = 10 km/h (DVB-RCS, HPAV, CMMB, DTMB)
changes occurs at f
chng
= 22 Hz. These scenarios result in
different reconfiguration probabilities, whose impact on BER
performance is addressed in Section V.
The reconfiguration memory is organized as a circular
buffer: two sets of pointers are used to manage reading and
writing operations. The Start of Current Configuration (SCC)
pointer and the End of Current Configuration (ECC) pointer
delimit the memory blocks that are currently being used. A
Read Pointer (RP) is used to retrieve the data during the
decoding process, as shown in Fig. 2.(a). The Start of Future
Configuration (SFC) and End of Future Configuration (EFC)
pointers are instead used concurrently with the Write Pointer
(WP) to delimit the locations that are going to be used to store
the new configuration data.
The reconfiguration of the considered decoder to switch
from the code currently processed (C
1
) to a new one (C
2
) can
be overlapped with the decoding of both current and new code,
provided that enough locations are free in the configuration
memories. In particular, part of the configuration process can
be concurrent with the decoding of one or more frames of
C
1
; if necessary, another portion of the configuration can be
scheduled during the first iteration of the new code C
2
. Finally,
in case the overlap with decoding activity is not sufficient to
complete the whole configuration, a further option is pausing
the decoder by skipping one or more iterations on the last
received frame for C
1
and using the available time, before
starting the decoding of the new frame encoded with C
2
.
Let us define B as the size of the location buffer available at
each PE to store configuration data, t
it1
and t
it2
as the duration
in clock cycles of a single decoding iteration for codes C
1
and
C
2
. Moreover, l
c1
and l
c2
express the number of locations
required to store configurations of codes C
1
and C
2
at each
PE, and n
it1
and n
it2
their iteration numbers.
In the considered architecture, the duration of one decoding
iteration t
it
expressed in clock cycles is directly proportional
to the number of memory locations a PE has to read throughout
the decoding process, and consequently to the number of
used locations in the reconfiguration memory (l
c
). Though the
actual relationship between t
it
and l
c
is affected by memory
scheduling and ratio between PE and NoC clock frequencies,
this analysis is carried out with the worst-case assumption
that the reconfiguration memory is read at every clock cycle
of each iteration, setting l
c
= t
it
for both C
1
and C
2
codes.
We define five phases Φ
i
, i = 1, 2, 3, 4, 5 in the config-
uration process and for each phase we identify i) t
Φ
i
a
as
the number of clock cycles available during phase Φ
i
, and
ii) l
Φ
i
a
= N
b
· t
Φ
i
a
/P as the number of locations in each
reconfiguration memory that can be written in t
Φ
i
a
clock cycles.
Φ
1
In the reconfiguration from code C
1
to code C
2
, l
c1
words
must be replaced with l
c2
new words. The first part of the
configuration can be scheduled during the initial n
it1
− 1
decoding iterations on C
1
and therefore the available time
is t
Φ
1
a
= (n
it1
−1)·t
it1
; in this range of time a maximum
of l
Φ
1
a
=
N
b
P
· (n
it1
− 1) · t
it1
words can be loaded
into each buffer. However, assuming that the buffer size
is larger than l
c1
, we define B − l
c1
as the number of
unused memory blocks in current configuration for code
C
1
. Therefore, the actual number of locations written in
Φ
1
is the minimum between B − l
c1
and l
Φ
1
a
. The SFC
pointer is thus initialized as ECC (Fig. 2.(b)).
Φ
2
During the last iteration on C
1
, every memory location
between SCC and the current position of RP is available
for reconfiguration. This means that up to l
c1
locations
are available for receiving configuration words for C
2
.
However, this has to be done during a single iteration,
and therefore t
Φ
2
a
= t
it1
cycles are available. During these
cycles, up to l
Φ
2
a
=
N
b
P
· t
it1
words can be loaded.
Φ
3
As mentioned before, part of the configuration can be
overlapped with the first decoding iteration on C
2
code.
SCC is initialized as SFC, and RP will take the duration
of a full iteration to arrive to ECC (Fig. 2.(c)). The
available time is t
Φ
3
a
= t
it2
and the maximum number of
words that can be loaded in this phase is l
Φ
3
a
=
N
b
P
· t
it2
.
Φ
4
In the event that previously listed phases are not sufficient
to complete the configuration, an early stopping in the
decoding of code C
1
can be scheduled to make available
additional cycles to be used for loading the remaining part
of the configuration words. We indicate the number of
cycles available in this phase as t
Φ
4
a
= t
stop
. The number
of words that can be loaded in Φ
4
is l
Φ
4
a
=
N
b
P
· t
stop
. As
one or more complete iterations are dropped in Φ
4
, t
stop
is a multiple of t
it1
, which can be formalized as
t
stop
= n
stop
· t
it1
, n
stop
= 0, 1, 2, 3, · · · (12)
Differently from the other four phases, Φ
4
affects the