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Proceedings ArticleDOI

VLSI implementation of fast convolution

Pankaj Katkar1, T N Sridhar1, G M Sharath1, S. Sivanantham1, K. Sivasankaran1 
01 Nov 2015-pp 1-5
TL;DR: This paper presents a direct method of reducing convolution processing time using hardware computing and implementations of discrete linear convolution of two finite length sequences by simplifying the convolution building blocks.
Abstract: Convolution is an algorithm widely used in image and video processing. Although its computation is simple, its implementation requires a high computational power and an intensive use of memory. This paper presents a direct method of reducing convolution processing time using hardware computing and implementations of discrete linear convolution of two finite length sequences. This implementation method is realized by simplifying the convolution building blocks.
Citations
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Journal ArticleDOI
23 Jun 2020-Sensors
TL;DR: This work proposes an AI-enabled framework for automating cleaning tasks through a Human Support Robot (HSR), and the overall cleaning process involves mobile base motion, door-handle detection, and control of the HSR manipulator for the completion of the cleaning tasks.
Abstract: The role of mobile robots for cleaning and sanitation purposes is increasing worldwide. Disinfection and hygiene are two integral parts of any safe indoor environment, and these factors become more critical in COVID-19-like pandemic situations. Door handles are highly sensitive contact points that are prone to be contamination. Automation of the door-handle cleaning task is not only important for ensuring safety, but also to improve efficiency. This work proposes an AI-enabled framework for automating cleaning tasks through a Human Support Robot (HSR). The overall cleaning process involves mobile base motion, door-handle detection, and control of the HSR manipulator for the completion of the cleaning tasks. The detection part exploits a deep-learning technique to classify the image space, and provides a set of coordinates for the robot. The cooperative control between the spraying and wiping is developed in the Robotic Operating System. The control module uses the information obtained from the detection module to generate a task/operational space for the robot, along with evaluating the desired position to actuate the manipulators. The complete strategy is validated through numerical simulations, and experiments on a Toyota HSR platform.

60 citations


Cites background from "VLSI implementation of fast convolu..."

  • ...Equation (2) explains the convolution operation for discrete time signals [37]....

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Journal ArticleDOI
TL;DR: This paper implemented the speed of discrete linear convolution using robust Vedic multiplier which is one of the fastest multipliers with two finitelength sequences.
Abstract: Convolution is an algorithm which is mainly used in video, audio and image processing. Convolution calculation is simple in steps however it consumes a lot of memory as well as power in the computational process. It is a mathematical algorithm which is also used in the applications like filtering, edge detection, de-noising, compression etc., as it can be exploit computational power. In this paper, we implemented the speed of discrete linear convolution using robust Vedic multiplier which is one of the fastest multipliers with two finitelength sequences. By implementing convolution with Vedic multiplier power, area and delay are reduced. This implementation process can be realized by simplifying the convolution building block.

1 citations


Cites background from "VLSI implementation of fast convolu..."

  • ...Now apply linearity property to the decomposed input signal and obtain the output response and it is simply added and this should afford us the total response of the system to any other given input signal [1]....

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  • ...For the processing of images, audio and video signals of complex mathematical computations are required, that consumes a lot of memory and increase the design complexity [1]....

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Proceedings ArticleDOI
04 Jun 2023
TL;DR: In this article , the RV-based convolution algorithm was proposed and applied to linear convolution, where every calculation is natively real-valued (RV) dot products.
Abstract: The Fast Fourier Transform (FFT)-based convolution is the most popular fast convolution algorithm. In past work, we developed the Discrete Hirschman Transform (DHT)-based convolution. When compared to the FFT-based convolution, our DHT-based convolution can reduce the computational complexity by a third. Recently, we developed a comprehensive DFT algorithm where every calculation is natively real-valued (RV) dot products. In this paper, we first apply the natively real-valued DFT to linear convolution. We call this method the RV-based convolution. The arithmetic analysis reveals that it efficiently reduces the operation counts. The algorithm is fast regardless of length.
References
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Proceedings ArticleDOI
25 Aug 1998
TL;DR: An implementation of a real time convolver, based on field programmable gate arrays (FPGAs) to perform the convolution operations, and the usage of external memory to implement a FIFO buffer and the partitioning of the Convolution matrix among several FPGAs to allow data parallel computation.
Abstract: We present an implementation of a real time convolver, based on field programmable gate arrays (FPGAs) to perform the convolution operations. Main characteristics of the proposed approach are the usage of external memory to implement a FIFO buffer where incoming pixels are stored and the partitioning of the convolution matrix among several FPGAs, in order to allow data parallel computation and to increase the size of the convolution kernel.

56 citations


"VLSI implementation of fast convolu..." refers background in this paper

  • ...The main aim of implementing convolution on FPGA is to design hardware that can reduce the convolution processing time and implement the discrete convolution of two finite length sequences (NXN) [1-3]....

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  • ...Index Terms— Convolution, Discrete linear convolution, FPGA I. INTRODUCTION The main aim of implementing convolution on FPGA is to design hardware that can reduce the convolution processing time and implement the discrete convolution of two finite length sequences (NXN) [1-3]....

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Journal ArticleDOI
TL;DR: This convolution method allows students to quickly verify their answers obtained by graphical convolution or from a computer program and easily extends to deconvolution and circular convolution as shown in this paper.
Abstract: Some students find convolution difficult to understand and compute when first learning. This paper presents a direct method of computing the discrete linear convolution of two finite length sequences. The approach is easy to learn because of the similarities to computing the multiplication of two numbers by a pencil and paper calculation. This method allows students to quickly verify their answers obtained by graphical convolution or from a computer program and easily extends to deconvolution and circular convolution as shown in this paper. When this convolution method was taught in a discrete signals and systems course, the students' understanding of convolution significantly improved.

38 citations


"VLSI implementation of fast convolu..." refers background in this paper

  • ...The reason that linear filtering is so important to signal processing is that it solves many problems and is relatively simple to describe mathematically[7]....

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Proceedings ArticleDOI
11 Oct 2009
TL;DR: This research is to prove the feasibility of an application specific integrated circuit (ASIC) that performs a convolution on an acquired image in real time and uses less power consumption and has a delay of 20ns from input to output using 32nm process library.
Abstract: This paper presents a direct method of reducing convolution processing time using hardware computing and implementations of discrete linear convolution of two finite length sequences (NXN). This implementation method is realized by simplifying the convolution building blocks. The purpose of this research is to prove the feasibility of an application specific integrated circuit (ASIC) that performs a convolution on an acquired image in real time. The proposed implementation uses a modified hierarchical design approach, which efficiently and accurately speeds up computation; reduces power, hardware resources, and area significantly. The efficiency of the proposed convolution circuit is tested by embedding it in a top level FPGA. Simulation and comparison to different design approaches show that the circuit uses only 5mw that saves almost 35% of area and is four times faster than what is implemented in [5]. In addition, the presented circuit uses less power consumption and has a delay of 20ns from input to output using 32nm process library. It also provides the necessary modularity, expandability, and regularity to form different convolutions for any number of bits.

31 citations


"VLSI implementation of fast convolu..." refers background in this paper

  • ...The main aim of implementing convolution on FPGA is to design hardware that can reduce the convolution processing time and implement the discrete convolution of two finite length sequences (NXN) [1-3]....

    [...]

  • ...Index Terms— Convolution, Discrete linear convolution, FPGA I. INTRODUCTION The main aim of implementing convolution on FPGA is to design hardware that can reduce the convolution processing time and implement the discrete convolution of two finite length sequences (NXN) [1-3]....

    [...]

Proceedings ArticleDOI
19 Jun 2001
TL;DR: Different optimisation techniques, exhausted search and simulated annealing, have been implemented for generating convolution in FPGAs with complex parameters of addition inputs e.g. correlation between inputs.
Abstract: Addition is an essential operation for convolution (or FIR filters). In FPGAs, addition should be carried out in a standard way employing ripple-carry adders (rather than carry-save adders), which complicates the search for an optimal adder structure as routing order has a substantial influence on the addition cost. Further, complex parameters of addition inputs have been considered e.g. correlation between inputs. These parameters are specified in different ways for different convolver architectures: multiplierless multiplication, look-up table based multiplication, distributed arithmetic. Furthermore, different optimisation techniques, exhausted search and simulated annealing, have been implemented. Otherwise, exhausted search should be employed for the number of the addition inputs n/spl les/8 or simulated annealing for n>8. Employing simulated annealing gives about 10-20% area reduction in comparison to the greedy algorithm. This paper is a part of the research on the AuToCon-automated tool for generating convolution in FPGAs.

19 citations


"VLSI implementation of fast convolu..." refers background in this paper

  • ...Convolutions on digital images are important since they represent operations more general than the operations that can be performed on analog images[4-6]....

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Proceedings ArticleDOI
01 Nov 2013
TL;DR: This paper modifies the HOT based convolution technique to make it more suitable for hardware realization, and shows almost 45% reduction in space compared to FFT convolution while maintaining similar MSE and slightly worse throughput.
Abstract: In this paper, a hardware efficient convolution implementation is proposed which is based on the Hirschman Optimal Transform (HOT) Previously, it has been shown theoretically that convolution based on HOT has major cost advantage over FFT based convolution, since, a K2 point HOT is based on a K-point DFT However, due to the complexity of the HOT convolution, it was not easily realizable on hardware This paper first modifies the HOT based convolution technique to make it more suitable for hardware realization Then, FFT based convolution and the proposed convolution are realized by using similar architectures To evaluate the effectiveness of the implementation, we compare the proposed convolution with the FFT convolution for a length of 256 The Mean Square Error (MSE), space requirements, and maximum throughput are used in the analysis of the implementations Field Programmable Gate Arrays (FPGAs) are used to implement the algorithms We have shown almost 45% reduction in space compared to FFT convolution while maintaining similar MSE and slightly worse throughput

8 citations


"VLSI implementation of fast convolu..." refers methods in this paper

  • ...An efficient hardware technique for linear convolution is explained in [9] and a cyclic convolution in [10]....

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