Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks
01 Jul 2010-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE)-Vol. 29, Iss: 7, pp 1056-1069
TL;DR: Results show that the cumulative distribution function of leakage current of ISCAS'85 circuits can be predicted accurately with the error in mean and standard deviation, compared to Monte Carlo-based simulations, being less than 1% and 2% respectively across a range of voltage and temperature values.
Abstract: Artificial neural networks (ANNs) have shown great promise in modeling circuit parameters for computer aided design applications. Leakage currents, which depend on process parameters, supply voltage and temperature can be modeled accurately with ANNs. However, the complex nature of the ANN model, with the standard sigmoidal activation functions, does not allow analytical expressions for its mean and variance. We propose the use of a new activation function that allows us to derive an analytical expression for the mean and a semi-analytical expression for the variance of the ANN-based leakage model. To the best of our knowledge this is the first result in this direction. Our neural network model also includes the voltage and temperature as input parameters, thereby enabling voltage and temperature aware statistical leakage analysis (SLA). All existing SLA frameworks are closely tied to the exponential polynomial leakage model and hence fail to work with sophisticated ANN models. In this paper, we also set up an SLA framework that can efficiently work with these ANN models. Results show that the cumulative distribution function of leakage current of ISCAS'85 circuits can be predicted accurately with the error in mean and standard deviation, compared to Monte Carlo-based simulations, being less than 1% and 2% respectively across a range of voltage and temperature values.
Citations
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29 Apr 2013
TL;DR: An analytical model is developed to predict the probability density function and covariance of temperatures and voltage droops of a die in the presence of the BTI and process variation and it is observed that for benchmark circuits, treating each aspect independently and ignoring their intrinsic interactions results in 16% over-design, translating to unnecessary yield and performance loss.
Abstract: In nano-scale regime, there are various sources of uncertainty and unpredictability of VLSI designs such as transistor aging mainly due to Bias Temperature Instability (BTI) as well as Process-Voltage-Temperature (PVT) variations. BTI exponentially varies by temperature and the actual supply voltage seen by the transistors within the chip which are functions of leakage power. Leakage power is strongly impacted by PVT and BTI which in turn results in thermal-voltage variations. Hence, neglecting one or some of these aspects can lead to a considerable inaccuracy in the estimated BTI-induced delay degradation. However, a holistic approach to tackle all these issues and their interdependence is missing. In this paper, we develop an analytical model to predict the probability density function and covariance of temperatures and voltage droops of a die in the presence of the BTI and process variation. Based on this model, we propose a statistical method that characterizes the life-time of the circuit affected by BTI in the presence of process-induced temperature-voltage variations. We observe that for benchmark circuits, treating each aspect independently and ignoring their intrinsic interactions results in 16% over-design, translating to unnecessary yield and performance loss.
30 citations
Cites background from "Voltage and Temperature Aware Stati..."
...BTI consists of two different phases: • Stress: When PMOS (NMOS) transistor is under negative (positive) bias, some interface traps are generated at the interface of Si-dielectric resulting in an increase in threshold voltage of the transistor....
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TL;DR: This paper proposes a methodology to discover the romized code whose access is protected by the virtual machine, which uses a hooked code in an indirection table to gain access to the real processor, thus allowing to run a shell code written in 8051 assembly language.
Abstract: Attacks on smart cards can only be based on a black box approach where the code of cryptographic primitives and operating system are not accessible. To perform hardware or software attacks, a white box approach providing access to the binary code is more efficient. In this paper, we propose a methodology to discover the romized code whose access is protected by the virtual machine. It uses a hooked code in an indirection table. We gained access to the real processor, thus allowing us to run a shell code written in 8051 assembly language. As a result, this code has been able to dump completely the ROM of a Java Card operating system. One of the issues is the possibility to reverse the cryptographic algorithm and all the embedded countermeasures. Finally, our attack is evaluated on different cards from distinct manufacturers.
19 citations
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...3 Temperature analysis [21,27,41]...
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TL;DR: A variability-aware machine learning (ML) approach that predicts variations in the key electrical parameters of 3-D NAND Flash memories caused by various sources of variability and verified the accuracy, efficiency, and generality of artificial neural network (ANN) algorithm-based ML systems.
Abstract: This article proposes a variability-aware machine learning (ML) approach that predicts variations in the key electrical parameters of 3-D NAND Flash memories. For the first time, we have verified the accuracy, efficiency, and generality of the predictive impact factor effects of artificial neural network (ANN) algorithm-based ML systems. ANN-based ML algorithms can be very effective in multiple-input and multiple-output (MIMO) predictions. Therefore, changes in the key electrical characteristics of the device caused by various sources of variability are simultaneously and integrally predicted. This algorithm benchmarks 3-D stochastic TCAD simulation, showing a prediction error rate of less than 1%, as well as a calculation cost reduction of over 80%. In addition, the generality of the algorithm is confirmed by predicting the operating characteristics of the 3-D NAND Flash memory with various structural conditions as the number of layers increases.
17 citations
Cites methods from "Voltage and Temperature Aware Stati..."
...As shown in Table II, the ANN algorithm structure has five layers, which are referred to in order as the input, first hidden, second hidden, third hidden, and output layers [12]–[15]....
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06 Apr 2020
TL;DR: This work investigated process variation effect of 3D NAND flash memory cell, especially about geometric variation using a machine learning (ML) model, which has multi-input and multi-output (MIMO) structure and deep hidden layers to train and predict complex data of process variation.
Abstract: We investigated process variation effect of 3D NAND flash memory cell, especially about geometric variation using a machine learning (ML) model. Geometric variability sources impact on variation of device's electrical parameters such as threshold voltage $(\mathbf{V}_{\mathbf{t}})$ , subthreshold swing (SS), transconductance $(\mathbf{g}_{\mathbf{m}})$ and on-current $(\mathbf{I}_{\mathbf{on}})$ . All these data were analyzed with 3D stochastic Technology Computer-Aided Design (TCAD) simulation and trained through ML model, which is composed of artificial neural network (ANN). The model has multi-input and multi-output (MIMO) structure and deep hidden layers to train and predict complex data of process variation. In order to make ML model more accurate, simulation for constructing training data set was carried out with a large number of random unit cells, which are cut from various strings. The completed ML model was tested with random test data set which had not been used for training to prove its accuracy. Through the test process, ML model showed the error of up to 5% and proved the accuracy of prediction.
14 citations
TL;DR: A single delay model of logic gate using neural network which comprehensively captures process, voltage, and temperature variation along with input slew and output load is proposed and shown how the model can be used to derive sensitivities required for linear SSTA for an arbitrary voltage and temperature.
Abstract: With the emergence of voltage scaling as one of the most powerful power reduction techniques, it has been important to support voltage scalable statistical static timing analysis (SSTA) in deep submicrometer process nodes. In this paper, we propose a single delay model of logic gate using neural network which comprehensively captures process, voltage, and temperature variation along with input slew and output load. The number of simulation programs with integrated circuit emphasis (SPICE) required to create this model over a large voltage and temperature range is found to be modest and 4t less than that required for a conventional table-based approach with comparable accuracy. We show how the model can be used to derive sensitivities required for linear SSTA for an arbitrary voltage and temperature. Our experimentation on ISCAS 85 benchmarks across a voltage range of 0.9-1.1 V shows that the average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.85%. The errors in predicting the 99% and 1% probability point are 1.31% and 1%, respectively, with respect to SPICE. The two potential applications of voltage-aware SSTA have been presented, i.e., one for improving the accuracy of timing analysis by considering instance-specific voltage drops in power grids and the other for determining optimum supply voltage for target yield for dynamic voltage scaling applications.
12 citations
Cites background from "Voltage and Temperature Aware Stati..."
...Recently, it has been shown in [28] that NNs, with a small modification to their kernel, are amenable to derivation of analytical formulae for the means of their outputs in terms of the input variables....
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References
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TL;DR: The proposed methods are effective in predicting the probability distribution of total chip leakage, and it is shown that ignoring spatial correlations can underestimate the standard deviation of full-chip leakage power.
Abstract: In this article, we present a method to analyze the total leakage current of a circuit under process variations, considering interdie and intradie variations as well as the effect of the spatial correlations of intradie variations. The approach considers both the subthreshold and gate tunneling leakage power, as well as their interactions. With process variations, each leakage component is approximated by a lognormal distribution, and the total chip leakage is computed as a sum of the correlated lognormals. Since the lognormals to be summed are large in number and have complicated correlation structures due to both spatial correlations and the correlation among different leakage mechanisms, we propose an efficient method to reduce the number of correlated lognormals for summation to a manageable quantity. We do so by identifying dominant states of leakage currents and taking advantage of the spatial correlation model and input states at the gates. An improved approach utilizing the principal components computed from spatially correlated process parameters is also proposed to further improve runtime efficiency. We show that the proposed methods are effective in predicting the probability distribution of total chip leakage, and that ignoring spatial correlations can underestimate the standard deviation of full-chip leakage power.
45 citations
"Voltage and Temperature Aware Stati..." refers background or methods in this paper
...From neural network theory [20] it is well known that the activation function, φ(x), should satisfy two conditions....
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...…the covariance evaluation for the variance term [4], i.e., 2Note that G represents the inter-die and spatially correlated intra-die component. without conditioning on the global parameters, the variance of the total leakage (X) in (4) is Var(X) = N∑ i=1 Var(Xi) + 2 N∑ i=1 N∑ j=i+1 Cov(Xi, Xj)....
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...…precise we also include the dependence on supply voltage (V ) and temperature (T ) µCkt(V, T ) = E[E[X(V, T )/G]] (14) = E ⎡ ⎣ M∑ j=1 βjµj(G, V, T ) ⎤ ⎦ (15) σ2Ckt(V, T ) = E [ Var(X(V, T )/G) ] + Var(E(X(V, T )/G)) (16) = E ⎡ ⎣ M∑ j=1 γ2j σ 2 j (G, V, T ) ⎤ ⎦ + Var ⎛ ⎝ M∑ j=1 βjµj(G, V, T ) ⎞ ⎠ ....
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...However, as mentioned before, ANNs can serve as excellent models to capture the dependence of leakage on process, voltage, and temperature (PVT) over a large range of non-linearities [15], [19]....
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...Existing leakage analysis frameworks use a simple model for a logic gate’s leakage consisting of an exponential of a linear or quadratic polynomial in the parameters (length, oxide thickness, threshold voltage) [4], [10], [11]....
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TL;DR: The dependence behavior among the process variability, leakage power consumption, and thermal profile construction are established to effectively extract a reliable statistical thermal profile over a die at the microarchitectural level.
Abstract: The nonuniform substrate thermal profile and process variations are two major concerns in the present-day ultra-deep submicrometer designs. To correctly predict performance/ leakage/reliability measures and address any yield losses during the early stages of design phases, it is desirable to have a reliable thermal estimation of the chip. However, the leakage power sources vary greatly due to process variations and temperature, which result in significant variations in the hotspot and thermal profile formation in very large scale integration chips. Traditionally, no leakage variations have been considered during full-chip thermal analysis. In this paper, the dependence behavior among the process variability, leakage power consumption, and thermal profile construction are established to effectively extract a reliable statistical thermal profile over a die at the microarchitectural level. Knowledge of this is the key to the design and analysis of circuits. The probability density functions of temperatures are extracted while considering the leakage variations due to the gate-length and oxide-thickness variations and while accounting for the coupling between the temperature and the total leakage. Two applications of the developed analyzer are investigated, namely, the evaluation of the hotspots' relocations and the total full-chip power estimation. Finally, the accuracy and efficiency of the developed analyzer are validated by comparisons with Monte Carlo simulations.
41 citations
"Voltage and Temperature Aware Stati..." refers background in this paper
...The random variable takes on the same value for all the gates within the region....
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TL;DR: The application of artificial neural networks to accurately capture the nonlinear mappings between parameters and performance to speed up the analysis of high-speed interconnect systems is described.
Abstract: In designing robust high-speed interconnect systems, the effects of parameter variations on system performance must be studied using statistical analyses. These analyses require repetitive circuit simulations to account for the randomness in parameter values caused by manufacturing and environmental changes. An accurate modeling technique is also essential for capturing the nonlinear relationships between channel parameters and performance. In this paper, the application of artificial neural networks to accurately capture the nonlinear mappings between parameters and performance to speed up the analysis of high-speed interconnect systems is described. An efficient set of data that uses a few simulations or experiments based on orthogonal arrays is proposed to train the neural network. The neural network can then serve to accurately and efficiently generate performance distributions. The usefulness and accuracy of the proposed approach is verified using an extreme data rate memory system that operates at a data rate of 3.2 Gb/s. The histograms and descriptive statistics of the eye height and timing jitter are compared with those obtained from traditional Monte Carlo, regression model, and worst case analyses
41 citations
"Voltage and Temperature Aware Stati..." refers background in this paper
...The heat dissipated by a block depends on its activity besides its leakage....
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TL;DR: A new chip-level statistical method to estimate the total leakage current in the presence of within-die and die-to-die variability is presented and an integrated approach to accurately estimate the yield loss when both frequency and power limits are imposed on a design is presented.
Abstract: In addition to traditional constraints on frequency, leakage current has emerged as a stringent constraint in modern processor designs. Since leakage current exhibits a strong inverse correlation with circuit delay, effective parametric yield prediction must consider the dependence of leakage current on frequency. In this paper, a new chip-level statistical method to estimate the total leakage current in the presence of within-die and die-to-die variability is presented. A closed-form equation for total chip leakage that models the dependence of the leakage current distribution on different process parameters is developed. The proposed analytical expression is obtained directly from pertinent design information and includes both subthreshold and gate leakage currents. Using this model, an integrated approach to accurately estimate the yield loss when both frequency and power limits are imposed on a design is then presented. The proposed method demonstrates the importance of considering both these limiting factors while calculating the yield of a lot
33 citations
"Voltage and Temperature Aware Stati..." refers background or methods in this paper
...Hence, we develop our framework for the ANN-based leakage model, i.e., we demonstrate how the expectations in (15) and (17) can be evaluated efficiently for the ANN-based leakage model....
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...Hence, even small variations in these show up as a large variation in the leakage current, with Borkar et al. in [3] reporting up to 20× variation in the leakage of manufactured chips....
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04 Jun 2007
TL;DR: This paper develops a fast approach to analyze the state-dependent total leakage power of a large circuit block, considering Ijunc, sub-threshold leakage (Isub), and gate oxide leakage (Igate), and proposes the algorithm to estimate the full-chip leakage power with consideration of both Gaussian and non- Gaussian parameter distributions.
Abstract: In this paper we address the the growing issue of junction tunneling leakage (Ijunc) at the circuit level. Specifically, we develop a fast approach to analyze the state-dependent total leakage power of a large circuit block, considering Ijunc, sub-threshold leakage (Isub), and gate oxide leakage (Igate). We then propose our algorithm to estimate the full-chip leakage power with consideration of both Gaussian and non- Gaussian parameter distributions, capturing spatial correlations using a grid-based model. Experiments on ISCAS85 benchmarks demonstrate that the estimated results are very accurate and efficient. For a circuit with G gates, the complexity of our approach is O(G).
16 citations
"Voltage and Temperature Aware Stati..." refers background in this paper
...However, as mentioned before, ANNs can serve as excellent models to capture the dependence of leakage on process, voltage, and temperature (PVT) over a large range of non-linearities [15], [19]....
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