Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations
04 Jan 2008-pp 685-691
TL;DR: This work investigates the feasibility of developing a comprehensive gate delay and slew models which incorporates output load, input edge slew, supply voltage, temperature, global process variations and local process variations all in the same model.
Abstract: We investigate the feasibility of developing a comprehensive gate delay and slew models which incorporates output load, input edge slew, supply voltage, temperature, global process variations and local process variations all in the same model. We find that the standard polynomial models cannot handle such a large heterogeneous set of input variables. We instead use neural networks, which are well known for their ability to approximate any arbitrary continuous function. Our initial experiments with a small subset of standard cell gates of an industrial 65 nm library show promising results with error in mean less than 1%, error in standard deviation less than 3% and maximum error less than 11% as compared to SPICE for models covering 0.9- 1.1 V of supply, -40degC to 125degC of temperature, load, slew and global and local process parameters. Enhancing the conventional libraries to be voltage and temperature scalable with similar accuracy requires on an average 4x more SPICE characterization runs.
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18 Aug 2010
TL;DR: A system architecture, measuring and modeling techniques, and algorithms for on-line power and energy optimization and thermal management, and linear programming and interpolation to calculate the temperature at any arbitrary point of the integrated circuit are developed.
Abstract: We have developed a system architecture, measuring and modeling techniques, and algorithms for on-line power and energy optimization and thermal management. The starting point for our approach is a simple and small gate-level network that can be used for real-time and low overhead measurement of temperature on chip positions where our network gates are placed. We use linear programming and interpolation to calculate the temperature at any arbitrary point of the integrated circuit. The periodic calculations of the temperature are used to estimate locally dissipated energies, which are consequently used to derive the most efficient use of operational times to minimize the overall leakage energy. All concepts and algorithms are experimentally validated using a simulation platform that consists of the Alpha 21364 processor and the SPEC benchmarks.
16 citations
TL;DR: A single delay model of logic gate using neural network which comprehensively captures process, voltage, and temperature variation along with input slew and output load is proposed and shown how the model can be used to derive sensitivities required for linear SSTA for an arbitrary voltage and temperature.
Abstract: With the emergence of voltage scaling as one of the most powerful power reduction techniques, it has been important to support voltage scalable statistical static timing analysis (SSTA) in deep submicrometer process nodes. In this paper, we propose a single delay model of logic gate using neural network which comprehensively captures process, voltage, and temperature variation along with input slew and output load. The number of simulation programs with integrated circuit emphasis (SPICE) required to create this model over a large voltage and temperature range is found to be modest and 4t less than that required for a conventional table-based approach with comparable accuracy. We show how the model can be used to derive sensitivities required for linear SSTA for an arbitrary voltage and temperature. Our experimentation on ISCAS 85 benchmarks across a voltage range of 0.9-1.1 V shows that the average error in mean delay is less than 1.08% and average error in standard deviation is less than 2.85%. The errors in predicting the 99% and 1% probability point are 1.31% and 1%, respectively, with respect to SPICE. The two potential applications of voltage-aware SSTA have been presented, i.e., one for improving the accuracy of timing analysis by considering instance-specific voltage drops in power grids and the other for determining optimum supply voltage for target yield for dynamic voltage scaling applications.
12 citations
Cites background or methods from "Voltage and Temperature Scalable Ga..."
...Hence, we have used NN with a single hidden layer as the modeling template in this paper [20]....
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...This paper is an extension of the work published in [20]....
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01 Nov 2010
TL;DR: This work presents the first sensor network architecture to monitor integrated circuits (IC) thermal and energy activity, which consists of a set of simple gates, which are superimposed over the actual design of any IC.
Abstract: We present the first sensor network architecture to monitor integrated circuits (IC) thermal and energy activity. The sensor network consists of a set of simple gates, which are superimposed over the actual design of any IC. The sensing network and the actual IC design are completely disjoint in order to enable their simultaneous operation. Since the delay of gates is proportional to their temperature, we can obtain temperature of the network gates, by measuring the delay of the gates in the self-sensing network. Once we measured the delay of the circuit, we use CMOS temperature-delay relation and linear programming formulation to calculate the temperature at any point on the chip. High resolution (spatial and temporal) temperature monitoring allows several run-time optimizations. Protecting shared processors from permanent localized damage through rapid creation of hot spots and efficient accounting of the available energy supply are among two main applications of our IC sensor network.
11 citations
09 Mar 2020
TL;DR: This paper presents a method for dynamic gate delay modeling on graphics processing unit (GPU) accelerators which is based on polynomial approximation with offline statistical learning using regression analysis, providing glitch-accurate switching activity information for gates and designs under varying supply voltages with negligible memory and performance impact.
Abstract: Timing validation of systems with adaptive voltage-and frequency scaling (AVFS) requires an accurate timing model under multiple operating points Simulating such a model at gate level is extremely time-consuming, and the state-of-the-art compromises both accuracy and compute efficiency This paper presents a method for dynamic gate delay modeling on graphics processing unit (GPU) accelerators which is based on polynomial approximation with offline statistical learning using regression analysis It provides glitch-accurate switching activity information for gates and designs under varying supply voltages with negligible memory and performance impact Parallelism from the evaluation of operating conditions, gates and stimuli is exploited simultaneously to utilize the high arithmetic computing throughput of GPUs This way, large-scale design space exploration of AVFS-based systems is enabled Experimental results demonstrate the efficiency and accuracy of the presented approach showing speedups of three orders of magnitude over conventional time simulation that supports static delays only
7 citations
Cites methods from "Voltage and Temperature Scalable Ga..."
...Besides common look-up table based approaches, analytical models with enclosed delay formulas [16–19] and delay approximation techniques [20, 21] were developed....
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...Prior normalization of the parameters is used to avoid over-fitting during regression [21]....
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...Another approximation approach based on machinelearning was proposed in [21]....
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...Note that although this work utilizes polynomials for the delay calculation [20], analytical models [17, 18] and other types of approximations [21] can be applied as well....
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Dissertation•
01 Jun 2009
2 citations
References
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TL;DR: It is shown that standard multilayer feedforward networks with as few as a single hidden layer and arbitrary bounded and nonconstant activation function are universal approximators with respect to L p (μ) performance criteria, for arbitrary finite input environment measures μ.
5,593 citations
"Voltage and Temperature Scalable Ga..." refers background or methods in this paper
...Characterization of the other gates in the library is on going and we expect the neural network model to work as well for those based on the theory [4] and our experience with the gates shown in the figures....
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...Since the model works with acceptable error bounds at all the nine corners, we expect it to work well at any intermediate point based on the interpolation properties of the network [4]....
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...Neural networks have been used for over a decade in pattern recognition applications [3] [4]....
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02 Jun 2003
TL;DR: Process, voltage and temperature variations; and their impact on circuit and microarchitecture; and possible solutions to reduce the impact of parameter variations and to achieve higher frequency bins are presented.
Abstract: Parameter variation in scaled technologies beyond 90nm will pose a major challenge for design of future high performance microprocessors. In this paper, we discuss process, voltage and temperature variations; and their impact on circuit and microarchitecture. Possible solutions to reduce the impact of parameter variations and to achieve higher frequency bins are also presented.
1,503 citations
"Voltage and Temperature Scalable Ga..." refers background in this paper
...Due to technology scaling, a large number of process related effects force a wide spread in process parameters, in turn causing a large variation in the chip’s delay and power [1] [10] [11]....
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TL;DR: An efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay considering both inter-die and intra- die variations, while accounting for the effects of spatial correlations of intra-die parameter variations, is presented.
Abstract: Process variations are of increasing concern in today's technologies, and they can significantly affect circuit performance An efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay considering both inter-die and intra-die variations, while accounting for the effects of spatial correlations of intra-die parameter variations, is presented The procedure uses a first-order Taylor series expansion to approximate the gate and interconnect delays Next, principal component analysis (PCA) techniques are employed to transform the set of correlated parameters into an uncorrelated set The statistical timing computation is then easily performed with a program evaluation and review technique (PERT)-like circuit graph traversal The run time of this algorithm is linear in the number of gates and interconnects, as well as the number of varying parameters and grid partitions that are used to model spatial correlations The accuracy of the method is verified with Monte Carlo (MC) simulation On average, for the 100 nm technology, the errors of mean and standard deviation (SD) values computed by the proposed method are 106% and -434%, respectively, and the errors of predicting the 99% and 1% confidence point are -246% and -099%, respectively A testcase with about 17 800 gates was solved in about 500 s, with high accuracy as compared to an MC simulation that required more than 15 h
276 citations
"Voltage and Temperature Scalable Ga..." refers background or methods in this paper
...Similarly, statistical delay models, which are usually linear [2] or quadratic [5], use such tables to store the delay sensitivity coefficients....
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...On the analysis side, Statistical Timing Analysis (SSTA) is being advocated for better insights into the chip’s delay spread instead of worst case corner based analysis [2] [5]....
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...A linear or quadratic sensitivity based delay model is quite accurate for a given supply, temperature, load and input slew [2] [5]....
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...Most of the existing literature on SSTA [2] [5] [10], only considers gate level variations, in effect having one random process parameter per gate....
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...These can be handled by partitioning the chip into grids and can be decorrelated using the technique in [2]....
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Book•
21 Jun 2005
TL;DR: The next generation of statistical models and techniques will be used to improve the quality of existing models and provide new insights into the determinants of yield and power.
Abstract: Statistical Models and Techniques- Statistical Timing Analysis- Statistical Power Analysis- Yield Analysis- Statistical Optimization Techniques
264 citations
"Voltage and Temperature Scalable Ga..." refers background in this paper
...Most of the existing literature on SSTA [2] [5] [10], only considers gate level variations, in effect having one random process parameter per gate....
[...]
...Due to technology scaling, a large number of process related effects force a wide spread in process parameters, in turn causing a large variation in the chip’s delay and power [1] [10] [11]....
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IBM1
TL;DR: A full chip leakage estimation technique which accurately accounts for power supply and temperature variations is presented and the results are demonstrated on large-scale industrial designs.
Abstract: Leakage power is emerging as a key design challenge in current and future CMOS designs. Since leakage is critically dependent on operating temperature and power supply, we present a full chip leakage estimation technique which accurately accounts for power supply and temperature variations. State of the art techniques are used to compute the thermal and power supply profile of the entire chip. Closed-form models are presented which relate leakage to temperature and VDD variations. These models coupled with the thermal and VDD profile are used to generate an accurate full chip leakage estimation technique considering environmental variations. The results of this approach are demonstrated on large-scale industrial designs.
255 citations