Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification
01 May 2015-IEEE Transactions on Very Large Scale Integration Systems (IEEE)-Vol. 23, Iss: 5, pp 801-809
TL;DR: An intellectual property protection scheme IPP_MRL is proposed for protection of manufacture-ready layout against unauthorized reuse and inclusion of Trojans, responses are resilient against process and temperature variation, but capable of detecting hardware Trojan.
Abstract: A manufacture-ready layout is vulnerable to misappropriation when it is either fabricated as a chip in a fabrication facility, or reused in a system-on-chip house. We propose an intellectual property protection (IPP) scheme IPP_MRL for protection of m anufacture- r eady l ayout against unauthorized reuse and inclusion of Trojans. The IPP_MRL inserts watermarks in the layout according to designer’s signature with an effect of tuning the delays at selected scan flip-flops. Certain dummy fills are reoriented in the neighborhood of selected net segments and it causes fine tuning of delay; certain other selected net segments are resized for coarse change in delay. The IPP_MRL not only verifies the watermark in the layout, but also captures its effect as delay fault-induced responses from the packaged chips, fabricated from the watermarked layout, by applying a faster test clock. Due to the controlled effect of watermarking on delay, responses are resilient against process and temperature variation, but capable of detecting hardware Trojan. The method is adaptive to device aging. The results for ISCAS’85 and ISCAS’89 benchmark circuits show that the overhead of watermarking on circuit delay is less than 0.05% and the probability of true false or false true can be at most $\sim 10^{-6}$ .
Citations
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01 Jan 2021
TL;DR: In this paper, the authors proposed a method to detect power dissipation attacks that may affect the green computing factor of a system or may drain the power budget of the system and cause early expiry of the computer system.
Abstract: Ensuring security for computer systems is of paramount importance. Analyzing various forms of attacks and defining strategies to prevent them is essential to generate trust among users. In general, to make a system reliable, system designers need to satisfy the basic three requirements, i.e. ensure confidentiality or prevent unauthorized observing of data or information, ensure integrity or prevent unauthorized change of data and ensure availability or facilitate authorized access to information or data at any instant of time and generate proper results within time. These three are commonly known as the CIA requirements [BT18]. However, with time, new attacks have arose like power dissipation attacks that may affect the green computing factor of a system or may drain the power budget of the system and cause early expiry of the system [Guh20, GMSC20]. Hence, it is the responsibility of system designers to analyze new and potential forms of threats that may arise with time and develop security strategies to mitigate them.
12 Oct 2014
TL;DR: In the emerging field of Intellectual property protection and security for ICs and SoCs with design reuse for shorter time-to-market, misappropriation may be categorized as unauthorized access or interception, generation of illegal copies and insertion of hardware trojan horse.
Abstract: In the emerging field of Intellectual property protection and security for ICs and SoCs with design reuse for shorter time-to-market (Fig. 1), misappropriation may be categorized as (i) unauthorized access or interception, (ii) generation of illegal copies and (iii) insertion of hardware trojan horse (Fig. 2).
10 Dec 2017
TL;DR: An improved Android applications protection system based on DEX block encryption and multi-file features checksum is proposed and experiment results show that the proposed system is more reliable than the commonly-used Android application protection systems when facing with attack tools such as APK Tools and IDA pro.
Abstract: Android is a widespread used embedded system. The number of Android applications has been rapidly growing. Because of Android open source policy and limited application security mechanism, Android applications are confronted with many serious security threats. By malicious reverse and illegal tampering, thousands of Android applications have been infected and millions of users have been exposed to dangers. In this paper, we proposed an improved Android applications protection system based on DEX block encryption and multi-file features checksum. Experiment results show that the proposed system is more reliable than the commonly-used Android application protection systems when facing with attack tools such as APK Tools and IDA pro.
References
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09 Jun 2008
TL;DR: This paper discusses how a technique for precisely measuring the combinational delay of an arbitrarily large number of register-to-register paths internal to the functional portion of the IC can be used to provide the desired authentication and design alteration detection.
Abstract: New attacker scenarios involving integrated circuits (ICs) are emerging that pose a tremendous threat to national security. Concerns about overseas fabrication facilities and the protection of deployed ICs have given rise to methods for IC authentication (ensuring that an IC being used in a system has not been altered, replaced, or spoofed) and hardware Trojan Horse (HTH) detection (ensuring that an IC fabricated in a nonsecure facility contains the desired functionality and nothing more), but significant additional work is required to quell these treats. This paper discusses how a technique for precisely measuring the combinational delay of an arbitrarily large number of register-to-register paths internal to the functional portion of the IC can be used to provide the desired authentication and design alteration (including HTH implantation) detection. This low-cost delay measurement technique does not affect the main IC functionality and can be performed at-speed at both test-time and run-time.
316 citations
"Watermarking in Hard Intellectual P..." refers background or methods in this paper
...In SoC company, a malicious designer may generate additional copies of the layout for reselling or redesign its interface for extracting information from it [8]....
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...The technique in [8] precisely measures actual combinational delay of large number of paths to detect the presence of a HTH, but is not effective for process invariant authentication of a hardware IP core....
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26 Jul 2009
TL;DR: A technique for recovery of characteristics of gates in terms of leakage current, switching power, and delay is introduced, which utilizes linear programming to solve a system of equations created using nondestructive measurements of power or delays to detect embedded HTHs.
Abstract: Hardware Trojan horses (HTHs) are the malicious altering of hardware specification or implementation in such a way that its functionality is altered under a set of conditions defined by the attacker. There are numerous HTHs sources including untrusted foundries, synthesis tools and libraries, testing and verification tools, and configuration scripts. HTH attacks can greatly comprise security and privacy of hardware users either directly or through interaction with pertinent systems and application software or with data. However, while there has been a huge research and development effort for detecting software Trojan horses, surprisingly, HTHs are rarely addressed. HTH detection is a particularly difficult task in modern and pending deep submicron technologies due to intrinsic manufacturing variability. Our goal is to provide an impetus for HTH research by creating a generic and easily applicable set of techniques and tools for HTH detection. We start by introducing a technique for recovery of characteristics of gates in terms of leakage current, switching power, and delay, which utilizes linear programming to solve a system of equations created using non-destructive measurements of power or delays. This technique is combined with constraint manipulation techniques to detect embedded HTHs. The effectiveness of the approach is demonstrated on a number of standard benchmarks.
263 citations
"Watermarking in Hard Intellectual P..." refers methods in this paper
...The gate level characterization-based techniques, see [10], use physical properties of the gates for characterization of ICs and process invariant detection of hardware Trojan....
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Book•
01 Jan 1998
TL;DR: This work presents a meta-modelling framework for designing and synthesising synthesis for Delay Fault Testability, and presents a number of case studies on Delay Testing that show the importance of knowing the architecture of the defect.
Abstract: Foreword. Preface. 1. Introduction. 2. Test Application Schemes for Testing Delay Defects. 3. Delay Fault Models. 4. Case Studies on Delay Testing. 5. Path Delay Fault Classification. 6. Delay Fault Simulation. 7. Test Generation for Path Delay Faults. 8. Design for Delay Fault Testability. 9. Synthesis for Delay Fault Testability. 10. Conclusions and Future Work. References. Index.
255 citations
TL;DR: It is demonstrated how reconfigurability can be exploited to eliminate the stated PUF limitations and how FPGA-based PUFs can be used for privacy protection.
Abstract: Physically unclonable functions (PUFs) provide a basis for many security and digital rights management protocols. PUF-based security approaches have numerous comparative strengths with respect to traditional cryptography-based techniques, including resilience against physical and side channel attacks and suitability for lightweight protocols. However, classical delay-based PUF structures have a number of drawbacks including susceptibility to guessing, reverse engineering, and emulation attacks, as well as sensitivity to operational and environmental variations.To address these limitations, we have developed a new set of techniques for FPGA-based PUF design and implementation. We demonstrate how reconfigurability can be exploited to eliminate the stated PUF limitations. We also show how FPGA-based PUFs can be used for privacy protection. Furthermore, reconfigurability enables the introduction of new techniques for PUF testing. The effectiveness of all the proposed techniques is validated using extensive implementations, simulations, and statistical analysis.
234 citations
"Watermarking in Hard Intellectual P..." refers methods in this paper
...Physically unclonable function (PUF)-based techniques, such as [7], authenticate each IC instance using delay/power characteristic of a PUF circuit....
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TL;DR: Watermarking-based IP protection as mentioned in this paper addresses IP protection by tracing unauthorized reuse and making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch, where a watermark is a mechanism for identification that is nearly invisible to human and machine inspection; difficult to remove; and permanently embedded as an integral part of the design.
Abstract: Digital system designs are the product of valuable effort and know-how. Their embodiments, from software and hardware description language program down to device-level netlist and mask data, represent carefully guarded intellectual property (IP). Hence, design methodologies based on IP reuse require new mechanisms to protect the rights of IP producers and owners. This paper establishes principles of watermarking-based IP protection, where a watermark is a mechanism for identification that is: (1) nearly invisible to human and machine inspection; (2) difficult to remove; and (3) permanently embedded as an integral part of the design. Watermarking addresses IP protection by tracing unauthorized reuse and making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch. We survey related work in cryptography and design methodology, then develop desiderata, metrics, and concrete protocols for constraint-based watermarking at various stages of the very large scale integration (VLSI) design process. In particular, we propose a new preprocessing approach that embeds watermarks as constraints into the input of a black-box design tool and a new postprocessing approach that embeds watermarks as constraints into the output of a black-box design tool. To demonstrate that our protocols can be transparently integrated into existing design flows, we use a testbed of commercial tools for VLSI physical design and embed watermarks into real-world industrial designs. We show that the implementation overhead is low-both in terms of central processing unit time and such standard physical design metrics as wirelength, layout area, number of vias, and routing congestion. We empirically show that the placement and routing applications considered in our methods achieve strong proofs of authorship and are resistant to tampering and do not adversely influence timing.
220 citations
Additional excerpts
...not support post-fab verification [2], [3]....
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