Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI
TL;DR: In this paper, a whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole chip ESDprotection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits.
Abstract: A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-/spl mu/m CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-/spl mu/m CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV.
Citations
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TL;DR: An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented and the solutions to overcome latchup issue in the SCR-based devices are discussed.
Abstract: An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented The history and evolution of SCR device used for on-chip ESD protection is introduced Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protection are reported Some modified device structures and trigger-assist circuit techniques to reduce the switching voltage of SCR-based devices are discussed The solutions to overcome latchup issue in the SCR-based devices are also discussed to safely apply the SCR-based devices for on-chip ESD protection in CMOS IC products
224 citations
Patent•
09 Nov 2007TL;DR: In this article, a low-voltage control without largely increasing the circuit layout area in a low power consumption structure is presented. But the authors focus on the case of low-speed control, where the region operates on voltages between a power supply voltage and a virtual reference potential.
Abstract: The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.
127 citations
Patent•
22 Jul 2003TL;DR: An ESD protection circuit includes an array of shunting devices coupled in parallel between an ESD bus (14) and a VSS bus (18) and distributed among the plurality of pad cells.
Abstract: An Electrostatic Discharge (ESD) protection circuit (9) includes a plurality of I/O and power supply pad cells (22, 40) that comprise external pads (31, 41) and circuitry requiring ESD protection. The protection circuit includes an array of shunting devices (36, 46) coupled in parallel between an ESD bus (14) and a VSS bus (18) and distributed among the plurality of pad cells. One or more trigger circuits (50) control the shunting devices. ESD events are coupled from any stressed pad onto two separate buses: the ESD bus which routes the high ESD currents to the positive current electrodes of the multiple shunting devices, and a Boost bus (12) which controls the trigger circuits. During an ESD event, the trigger circuits drive the control electrodes of the shunting devices to a voltage level greater than possible with prior art circuits, thereby reducing the on-resistance of the shunting devices.
112 citations
Patent•
TSMC1
TL;DR: An ESD protection circuit is connected to an integrated circuit to dissipate an electrostatic charge from an ESD source placed in contact with two terminals of the integrated circuit, to prevent damage to the integrated circuits as discussed by the authors.
Abstract: An ESD protection circuit is connected to an integrated circuit to dissipate an electrostatic charge from an ESD source placed in contact with two terminals of the integrated circuit to prevent damage to the integrated circuits. The ESD protection circuit has a ESD shunting circuit for shunting the electrostatic charge from integrated circuit. The ESD shunting circuit has a first port connected to one terminal of the integrated circuit, a second port connected to another terminal of the integrated circuit, and a third port. The ESD protection circuit additionally has an ESD detection circuit. The ESD detection circuit has a first input port connected to the one terminal of the integrated circuit, a second input port connected to the other terminal of the integrated circuit, and an output port connected to the third port of the ESD shunting circuit. When the ESD detection circuit detects the presence of the electrostatic charge from the ESD source, the ESD detection circuit generates an excess voltage at the third port that will damage the ESD shunting circuit. Finally The ESD protection circuit has a voltage clamping circuit connected between the third port of the ESD shunting circuit and one of the terminals of the integrated circuit to prevent the generation of the excess voltage at the third port of the ESD shunting circuit.
108 citations
TL;DR: In this article, the gate-driven effect and substrate-triggered effect on electrostatic discharge (ESD) robustness of CMOS devices are measured and compared, and the operation principles of gate-grounded design, gatedriven design, and substrate triggered design are explained clearly by energy-band diagrams.
Abstract: The gate-driven effect and substrate-triggered effect on electrostatic discharge (ESD) robustness of CMOS devices are measured and compared in this paper. The operation principles of gate-grounded design, gate-driven design, and substrate-triggered design on CMOS devices for ESD protection are explained clearly by energy-band diagrams. The relations between ESD robustness and the devices with different triggered methods are also explained by transmission line pulsing (TLP) measured results and energy-band diagrams. The turn-on mechanisms of nMOS devices with triggered methods are further verified using the emission microscope (EMMI) photographs of the nMOS devices under current stress. The experimental results confirm that the substrate-triggered design can effectively and continually improve ESD robustness of CMOS devices better than the gate-driven design. The human body model (HBM) ESD level of nMOS with a W/L of 400 /spl mu/m/0.8 /spl mu/m in a silicided CMOS process can be improved from the original 3.5 kV to over 8 kV by using the substrate-triggered design. The gate-driven design cannot continually improve the ESD level of the device in the same deep-submicron CMOS process.
89 citations
References
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TL;DR: In this paper, the trend in ESD robustness as a function of technology scaling, for feature sizes down to 0.25 /spl mu/m, have been experimentally determined using single finger nMOS transistors and full ESD protection circuits.
Abstract: The trends in ESD robustness as a function of technology scaling, for feature sizes down to 0.25 /spl mu/m, have been experimentally determined using single finger nMOS transistors and full ESD protection circuits. It is shown that as feature sizes are reduced, good ESD performance can be obtained provided the negative effects of the shallower junctions are offset by the positive effects of the reduction in the effective channel lengths. Hence, processes and protection circuits with feature sizes as small as 0.25 /spl mu/m can be developed without degrading ESD robustness. >
182 citations
"Whole-chip ESD protection design wi..." refers methods in this paper
...IC’s. Especially in the submicron CMOS technologies, the advanced processes greatly degrade the ESD robustness of CMOS IC’s [ 1 ], [2]....
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01 Mar 1992
TL;DR: In this article, a dynamic gate coupling effect that increases the electrostatic discharge (ESD) protection efficiency of NMOS output devices is reported and the design issues for optimum output ESD protection are also discussed.
Abstract: A dynamic gate coupling effect that increases the electrostatic discharge (ESD) protection efficiency of NMOS output devices is reported. The authors discuss the gate coupling phenomenon for NMOS transistors and its effect under ESD transient conditions. A dynamic gate-coupled device was studied to understand the gate coupling effect. The authors present the complete phenomena and results for nonsilicided devices as well as for silicided structures. The measured ESD stress results are given. The gate coupling effect and device operation under ESD are explained by using modeling and simulation results. The design issues for optimum output ESD protection are also discussed. >
169 citations
"Whole-chip ESD protection design wi..." refers background in this paper
...But, an NMOS device with a higher gate voltage or a longer turn-on time often causes a lower (secondary breakdown current) value [ 22 ], [23], because a shallow current flows through the channel surface of the NMOS....
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01 Jan 1995
TL;DR: In this article, an array of ESD protection methods have been developed and tested which depend on forward biased diodes and normal MOSFET conduction, which result in parts made in 0.8 and 0.6 /spl mu/m salicided technologies routinely passing their upper division spec. of /spl plusmn/4500 V HBM without any discernible increase in pin leakage.
Abstract: Because of leakage problems related to avalanche breakdown of salicided junctions, an array of ESD protection methods has been developed and tested which depend on forward biased diodes and normal MOSFET conduction. These methods include the case of multiple power supplies, the case where the pad voltage can exceed the power supply voltage, and the case where the pad voltage both exceeds the power supply voltage and the process voltage limit. These methods result in parts made in 0.8 and 0.6 /spl mu/m salicided technologies routinely passing our upper division spec. of /spl plusmn/4500 V HBM without any discernible increase in pin leakage. Also, split supply salicided parts pass 1 kV of CDM with no discernible pin leakage increase and 2 kV with pin leakage increase but within spec. (10 /spl mu/A).
142 citations
01 Jan 1995
TL;DR: In this article, the p-n-p transistor chains are made from floating n-wells in p-substrate CMOS and used for power supply ESD clamps.
Abstract: Biased and terminated p-n-p transistor chains are made from floating n-wells in p-substrate CMOS and used for power supply ESD clamps. The p-n-p gain may allow a compact termination circuit to be used, resulting in a stand-alone clamp. Bipolar p-n-p action accounts for unwanted low-voltage conduction as well as for very desirable clamping of power supply overvoltages. Bias networks are used to prevent excessive leakage at high temperature. These devices are becoming crucial to success in ESD product testing of CMOS integrated circuits.
96 citations
TL;DR: In this paper, the issues of protection between V/sub DD/ and V/ sub SS/ are discussed and examples of how protection circuit performance can be sensitive to internal chip layout, independent of its effective design.
Abstract: Input/output electrostatic discharge (ESD) circuit requirements call for good protection of the pin with respect to both the ground and the power bus pins. Although effective protection can be designed at the pin many cases of damage phenomena are known to occur internal to the chip beyond the protection circuit. Here, the issues of protection between V/sub DD/ and V/sub SS/ are discussed first. This is followed by examples of how protection circuit performance can be sensitive to internal chip layout, independent of its effective design. Several illustrative actual case studies are reported to emphasize the internal chip ESD phenomena and their adverse effects. >
92 citations
"Whole-chip ESD protection design wi..." refers background in this paper
...Besides the input or output ESD protection circuits placed around the input or output pads, some unexpected ESD damages are still found in the internal circuits of CMOS IC’s beyond the input or output ESD protection circuits [ 3 ]‐[11]....
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