IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 6, JUNE 2008 1341
Wideband Balun-LNA With Simultaneous Output
Balancing, Noise-Canceling and Distortion-Canceling
Stephan C. Blaakmeer, Member, IEEE, Eric A. M. Klumperink, Senior Member, IEEE,
Domine M. W. Leenaerts, Fellow, IEEE, and Bram Nauta, Fellow, IEEE
Abstract—An inductorless low-noise amplifier (LNA) with active
balun is proposed for multi-standard radio applications between
100 MHz and 6 GHz. It exploits a combination of a common-gate
(CG) stage and an admittance-scaled common-source (CS) stage
with replica biasing to maximize balanced operation, while simul-
taneously canceling the noise and distortion of the CG-stage. In
this way, a noise figure (NF) close to or below 3 dB can be achieved,
while good linearity is possible when the CS-stage is carefully op-
timized. We show that a CS-stage with deep submicron transistors
can have high IIP2, because the
cross-term in a two-di-
mensional Taylor approximation of the
( )
charac-
teristic can cancel the traditionally dominant square-law term in
the
( )
relation at practical gain values. Using standard
65 nm transistors at 1.2 V supply voltage, we realize a balun-LNA
with 15 dB gain, NF
3.5 dB and IIP2
+
20 dBm, while simul-
taneously achieving an IIP3
0 dBm. The best performance of
the balun is achieved between 300 MHz to 3.5 GHz with gain and
phase errors below 0.3 dB and
2 degrees. The total power con-
sumption is 21 mW, while the active area is only 0.01 mm
2
.
Index Terms—CMOS integrated circuits, distortion canceling,
linearity, low noise, low-noise amplifiers (LNAs), low-power elec-
tronics, noise canceling, noise cancellation, wideband LNA, wide-
band matching.
I. INTRODUCTION
U
PCOMING software-defined and multi-standard radio ar-
chitectures may cover all major communication bands in
use today up to 6 GHz [1]. This puts interesting demands on the
radio and its low-noise amplifier (LNA). The wanted frequency
span can be chopped into smaller bands which then can be pro-
cessed by several dedicated, possibly tuned, LNA circuits. The
other extreme is a single LNA, which then obviously needs to
have wide bandwidth. In contrast to a multi-LNA solution, the
single wideband LNA is flexible and efficient in terms of area,
power and costs. Single-ended input LNAs are preferred to save
I/O pins and because antennas and RF filters usually produce
single ended signals. On the other hand, differential signaling
in the receive chain is preferred in order to reduce second-order
distortion and to reject power supply and substrate noise. Thus,
at some point in the receive chain a balun is needed to convert
the single-ended RF signal into a differential signal. Off-chip
Manuscript received July 23, 2007; revised March 4, 2008.
S. C. Blaakmeer, E. A. M. Klumperink, and B. Nauta are with University of
Twente, CTIT Institute, IC Design Group, Enschede, The Netherlands (e-mail:
S.C.Blaakmeer@utwente.nl).
D. M. W. Leenaerts is with NXP Semiconductors, Research, 2525 AE Eind-
hoven, The Netherlands.
Digital Object Identifier 10.1109/JSSC.2008.922736
Fig. 1. The basic common-gate–common-source topology in which the noise
of the CG-transistor can be canceled.
baluns with low losses are typically narrowband so that several
baluns would be required in case of wideband operation. On the
other hand, wideband passive baluns typically have high loss,
degrading the overall NF of a receiver significantly.
Combining the balun and LNA functionality into a single in-
tegrated circuit seems an attractive option to realize a wideband
low-noise receiver front-end. However, only a few CMOS wide-
band LNA-balun combinations with sufficient low noise figure
for multiband receivers (3–4 dB) have been published [1]–[3].
These circuits all exploit the noise canceling topology published
in [4, Fig. 4b], shown in Fig. 1. This is one of the noise can-
celing topologies discussed in [5]. Although these circuits have
a single-ended input and differential output, the (im)balance of
the output signal is not reported. We will show that this imbal-
ance can be significant, e.g., about 6 dB in [1, Fig. 8a]. Next
to this, the circuits in [1]–[3] all use integrated inductors. As
in newer CMOS technologies the area-costs increase, area-con-
suming integrated inductors become increasingly expensive. Fi-
nally, we prefer to use baseline transistors at the standard supply
voltage of 1.2 V instead of thick oxide transistors at 1.8 V [2] or
2.5 V supply [1]. This is challenging with respect to achieving
sufficient gain and good linearity.
In this paper, we present an inductorless balun-LNA with a
well-balanced output signal, and will show that it can achieve
wideband amplification at low noise in a baseline 65 nm CMOS
process with standard 1.2 V supply voltage, while also achieving
good linearity. The measurements on this circuit were published
in [6]. This paper gives an in-depth analysis of the design op-
tions, the noise behavior and distortion behavior of the used
circuit topology. Furthermore, to the authors’ knowledge, this
is the first paper in which it is recognized that cross-terms in
the
characteristic of modern submicron CMOS
0018-9200/$25.00 © 2008 IEEE
1342 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 6, JUNE 2008
Fig. 2. Small signal equivalent of a CG-stage.
transistors can be exploited to obtain an amplifying stage with
low second-order distortion.
The balun-LNA circuit topology is depicted in Fig. 1. This
common-gate (CG) stage in parallel to a common-source (CS)
stage is a well-known structure. Actually, there are at least 15 to
20 year old references [7], [8, Figs. 2 and 3], and possibly even
older ones. Later, this structure has been used in the “micro-
mixer” circuit [9] and the LNA in [1]. However, all these circuits
use CG and CS devices with
identical size and bias. As will be
shown in Sections II and III, identical devices cannot simulta-
neously bring the benefits of output balancing, noise canceling
and distortion canceling. This paper provides insight in circuit
dimensioning trade-offs and reveals new ways to exploit the cir-
cuit to maximize performance. To this end, Section II derives
conditions for simultaneous output balancing, noise canceling
and distortion canceling. Section III details the noise analysis
and motivates why appropriate scaling of the CS-stage is needed
to exploit noise canceling most effectively and obtain a noise
figure in the order of 3 dB or lower. Apart from noise, the circuit
also simultaneously renders distortion canceling of the (CG-)
matching-device nonlinearity [4]. However, to benefit from this,
the CS-stage needs to have low distortion too. Therefore, we
analyze distortion in detail in Section IV, focusing on short
channel devices. The distortion generated by these devices is
not only due to nonlinearity of their transconductance
and
of their output conductance
, but also due to the depen-
dence of
on the drain-source bias voltage. We will show that
a (cross-) term describing this dependence can be used to cancel
the dominant second-order distortion due to
. Together with
the distortion canceling of the CG-stage this results in a high
overall IIP2. In Section V we describe the actual balun-LNA
circuit design, to validate theory and set an expectation for the
measurements. Section VI presents measurements and bench-
marks the LNA to previous designs, while Section VII presents
a summary and conclusions.
II. S
IMULTANEOUS BALANCING AND
NOISE/DISTORTION CANCELING
In the sections below we will briefly derive the conditions
for simultaneous balancing, noise canceling and distortion can-
celing. We will neglect capacitive effects for simplicity, and
verify the validity of this assumption later via measurements.
A more detailed discussion on high frequency limitations and
robustness for component variations can be found in [5].
A. Balancing (Balun Operation)
The common-gate stage in Fig. 2, biased with a current
source, has a straightforward relation between its voltage gain
and its input impedance . The signal current
flowing through the load resistor has to be equal
to the signal current flowing at the input
, as there is no
alternative path to ground. Thus,
(1)
As a result, the input impedance of the CG-stage can be ex-
pressed as
(2)
For an ideal transistor, having infinite output resistance, this
is obvious. In that case the input impedance can be written as
and the gain equals .
However, (1) and (2) are equally valid when the finite output
resistance and the body-effect of a real transistor are taken into
account.
For an impedance match at the input, the input impedance of
the CG-stage
should equal the source resistance ,
thus the gain of the CG stage becomes
(3)
To create a balun, the gain of the CS-stage in Fig. 1 should be
equal, but have opposite sign, thus,
(4)
B. Noise Canceling
The noise generated by the CG-transistor in Fig. 1 can be
represented by a current source
. This current generates both
a voltage at the input-node
and a fully
correlated anti-phase voltage at the CG-output
. The factor equals the voltage division between
the input resistance
and the source resistance ,
which equals 1/2 in case of impedance matching:
(5)
The noise at the CS-output equals the CG-output noise
, when the CS-gain
satisfies (4). Thus, the noise contribution of the CG-transistor
can be canceled, as it becomes a purely common-mode signal
at the differential output
. This proofs that simultaneously
balancing of the output signal and noise canceling is obtained.
C. Distortion Canceling
As derived in [4], not only the noise of the impedance
matching device is canceled, but also its nonlinearity, assuming
BLAAKMEER et al.: WIDEBAND BALUN-LNA WITH SIMULTANEOUS OUTPUT BALANCING, NOISE-CANCELING AND DISTORTION-CANCELING 1343
it can be modeled as a current source between drain and source,
controlled by the gate-source voltage. We will take this one
step further here, by also taking into account the influence
of the drain-source voltage on the drain current. This allows
the modeling of the nonlinear output conductance and other
second-order effects like Drain Induced Barrier Lowering
(DIBL), which become more prominent in modern CMOS
processes.
Fig. 2 shows a model of the CG-stage. Weakly nonlinear
behavior is assumed, modeled by a drain-source current
which depends nonlinearly on both voltage variations and
around their DC bias points.
1
The source signal
causes
a nonlinear drain-source current
which is converted into
a nonlinear voltage at the input
via the (linear) source
resistor
. The nonlinear input voltage can be written
as a Taylor expansion of the signal source voltage
:
(6)
where the
’s represent Taylor coefficients and contains all
unwanted nonlinear terms and the first Taylor coefficient
is defined in (5).
The output voltage of the CG-stage (see Fig. 2) can be written
as
(7)
where (6) is used. The output voltage of the CS-stage can be
written using (4) as
(8)
The difference in sign of the wanted signal
and unwanted
signal
in (7) and (8) can be exploited: after subtraction only
the linear signal remains
(9)
In conclusion, all noise and distortion currents generated
by the CG-transistor can be canceled, irrespective whether
produced due to nonlinearity of the transconductance or non-
linearity of the output conductance. The gain required in the
CS-stage to cancel the distortion products of the CG-transistor
equals the gain required to obtain output balancing, leading to
the conclusion that simultaneous balancing and cancellation of
unwanted noise and distortion currents of the CG transistor is
possible. As the distortion due to the CG-transistor is canceled,
while
is normally quite linear, the CS-stage will determine
the overall linearity of the complete LNA. The linearity of the
CS-stage will be analyzed in Section IV-B. The final noise
is determined by
together with the CS-stage, as will be
shown in the next section.
III. N
OISE ANALYSIS
In this section, we analyze the noise figure of the basic CG-CS
LNA (Fig. 1) for three different design options. To simplify
1
Also the body-effect can be accounted for, by observing that
v
=
0
v
for a CG-transistor with its bulk node
(
b
)
connected to ground.
the calculation, transistors are assumed to have infinite output
impedance and the bias current source of the CG-transistor is
assumed to be ideal. Furthermore only the thermal noise of the
resistors and of the transistors
is taken
into account assuming
, which is known to be opti-
mistic for short channel devices. These assumptions will over-
estimate the gain and underestimate the NF. However, the calcu-
lation is useful to compare the different design options and sim-
plifies comparison to previously published results using similar
assumptions. The output noise power of the circuit elements in
Fig. 1 can be calculated, and divided by the noise contribution
of the signal source, leading to the noise factor:
(10)
where the second part is the contribution from the CG-transistor,
the third part from the CS-transistor and the last part from the
load resistors, while the voltage gain
equals
(11)
Three different design options of the CG-CS circuit are now
considered, as follows.
1) The transconductances of the CS and CG transistors are
equal and the load resistors are equal, thus:
and (the traditional way to implement an
active balun [7], [8], using a CG-CS amplifier).
2) The transconductance of the CS transistor is
times bigger
than the CG-transconductance and the load resistors are
equal, thus:
and (design
option used in [1]).
3) The CS-transconductance is
times bigger than the
CG-transconductance and the CS-resistor is
times
smaller than the CG-resistor, thus:
and
(characterizes the design presented in this
paper).
The ratio of the voltage gain of the CS- and the CG-stage is
defined as the gain imbalance:
(12)
The noise figure, voltage gain
and gain imbalance
of the three design options are plotted versus the
impedance scaling factor
in Fig. 3. In all three cases the
CG-transconductance is assumed to be:
,to
have input impedance matching and
to have a
reasonable gain of the CG-stage.
Option 1) gives horizontal lines, as it does not depend on the
factor
. The NF equals 3.4 dB, the voltage gain 18.1 dB (8 )
and the output signal is perfectly balanced
dB .
Although the noise of the CG-transistor is fully canceled, this
effect is not exploited to achieve a NF below 3 dB. The noise
generated by the CS-stage is significant because of its low
1344 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 6, JUNE 2008
Fig. 3. Noise figure (NF), voltage gain
(
A
)
and gain imbalance
(
1A
)
versus impedance scaling factor ‘
n
’ for three different cases.
transconductance and the voltage division of
1/2 by
and magnifies its contribution.
Option 2) shows a decreasing NF and an increase in voltage-
gain with increasing
. These two positive effects are however
countered by an increase in gain imbalance. As
increases,
the voltage gain of the CS-stage gain increases whereas the
CG-voltage gain remains constant.
The last option, 3), shows an even faster decrease of NF
than in option 2). In contrast to option 2), the noise of the
CG-transistor is fully canceled. Next to this, the contribution of
the CS-transistor decreases with a factor
for increasing ,
whereas in option 2) this contribution decreases at a rate slower
than
. The voltage gain remains constant for option 3). Both
the transconductance and the resistance of the CS-stage are
scaled simultaneously (admittance scaling [10]). Thus the gain
of the CS-stage remains constant and no gain imbalance occurs,
i.e., the balun functionality is maintained for all values of
.
Now some more attention is given to design option 2)
as published in [1]. Both in the calculation above and in
[1] the load resistors have a value of
.
The transconductance-scaling factor in [1] is estimated to
be in the range
–3, using the square-law MOS-model
. This translates into a gain
imbalance between CG- and CS-stage of 6–9.5 dB and (10)
gives a NF between 2.8 and 2.5 dB. The remarkably low NF
reported in [1, Figure 8b] of about 2.2 dB is a simulation result
where
is assumed (instead of , or higher) [11].
In the abstract of [1] a much higher NF of 3–3.5 dB is given.
Overall, we conclude that admittance scaling of the CS-stage
(option 3) is the best way to achieve low noise figure in the
order of 3 dB or below, while simultaneously achieving good
output balancing. It is possible to get more gain using option 2
[1], but this comes at the cost of suboptimal noise behavior and
significant unbalance in the output signal.
IV. L
INEARITY ANALYSIS
In this section we will analyze the nonlinearity of the
balun-LNA proposed in the previous section and see how
we can exploit the distortion cancellation property. However,
before we do so, we first want to introduce the IIP2 problem of
wideband LNAs.
A. Linearity Requirements for Wideband Receivers
Like a narrowband zero-IF or near zero-IF receiver, a
wideband receiver is sensitive to the second-order intermod-
ulation product generated by an AM modulated carrier via
AM detection. However, a wideband receiver may also suffer
from second-order intermodulation generated by interferers
that have a sum or difference frequency equal to the wanted
RF-input signal. The response to a modulated carrier can be
suppressed by placing a high-pass filter (i.e., AC-coupling)
between the LNA-output and mixer-input and by driving and
designing the mixer in a well-balanced way [12]. However,
the intermodulation product generated at a frequency equal to
the frequency of the wanted signal cannot be separated from
the signal. Especially standards that operate on large band-
widths, like DVB-H (470–862 MHz) [13] or WiMedia UWB
(3.1–10.6 GHz) [14], have a high probability that a certain
combination of interferers renders an in-band intermodula-
tion product. A receiver designed for these standards should
have an LNA with sufficiently high IIP2 (and IIP3) in order
to handle strong interferers like WLAN (IEEE 802.11a/b/g)
and the GSM standards. The required intercept points depend
strongly on the assumed interferer scenario and the assumed
BLAAKMEER et al.: WIDEBAND BALUN-LNA WITH SIMULTANEOUS OUTPUT BALANCING, NOISE-CANCELING AND DISTORTION-CANCELING 1345
amount of pre-filtering of the interfering signals. For a Wi-
Media UWB receiver the required IIP2 is above
20 dBm and
IIP3 above
9 dBm as derived in [15, sec. II]. For a DVB-H
receiver, consider a GSM interferer (1.8 GHz,
30 dBm at
0.2 m distance) and a WLAN interferer (2.4 GHz,
20 dBm
at 1 m) that generate second-order intermodulation product
in the DVB-H band at 600 MHz. The received interferer
power levels will be
7 dBm (GSM) and 20 dBm (WLAN).
For a decrease in sensitivity of 3 dB, the maximum allow-
able interference level in a DVB-H receiver is
105 dBm
[13]. Without filtering the required IIP2 would become
IIP2
dBm .
Assuming that both (out-of-band) interferers can be filtered
with 35 dB attenuation brings the required IIP2 back to a more
realistic value of
22 dBm.
B. Distortion of the CS-Stage
As the distortion of the CG-stage can be canceled in the
parallel CG- and CS-stage amplifier (Section II-C), the dis-
tortion performance of the total amplifier is determined by
the distortion behavior of the CS stage. For distortion calcula-
tions often only the nonlinearity of the transconductance of a
transistor is taken into account. However, as in [16], [17], we
find that the nonlinearity of the output conductance cannot be
neglected anymore in modern CMOS processes. The drain cur-
rent
as function of the gate-source voltage and the
drain-source voltage
can be written as a two-dimensional
Taylor approximation:
(13)
where the Taylor coefficients can be derived from the large
signal relations between
, and :
(14)
Notice that in (13)
not only depends on powers of and
but also on cross-terms ( , , etc.) of and . The cross-
term
can be described as the dependence of the transconduc-
tance
on the drain-source bias voltage. One of the rea-
sons for this dependence is the drain induced barrier lowering
(DIBL) effect. The terms
, , etc. are higher order deriva-
tives of
. The cross-terms will prove to be very important for
the linearity in modern short-channel CMOS processes. In [18]
the importance of these cross-terms was shown for MESFET
transistors, which have linearity characteristics that are some-
what similar to MOSFETs. The linearity of a resistively loaded
CS-transistor (
and in Fig. 1) is calculated. The varia-
tion of the drain source voltage
is set by the output current
of the transistor
and the load resistor . Using this and
(13)
can be expressed in a Taylor approximation of :
(15)
Fig. 4.
V
and
I
versus
V
of a resistively loaded CS-stage.
with the following Taylor coefficients:
(16)
To demonstrate the importance of the coefficients in (16),
they have been derived from simulations. The circuit parame-
ters of the simulated CS-stage are:
m m
and
. MOS model 11 [19], known for its accurate
linearity modeling, is used for the transistor model. Fig. 4 shows
the drain-source current
and the drain-source voltage
versus the gate-source bias voltage . In the inset
of Fig. 5 the linear voltage gain
of the CS-stage versus
is plotted. The second-order coefficient is proportional
to the derivative of
, thus it equals 0 at the maximum gain
point (
at ). The three contributions that
sum up to
in (16) are also shown in Fig. 5. In the lower range
of
, where the transistor is in saturation, the second-order
distortion due to the cross-term
is in the same order (but
with opposite sign) as the second-order coefficient generated
by the transconductance nonlinearity
. These two terms
cancel each other around the maximum in gain
.
The contribution due to the output conductance
in this
range is small. As increases (and decreases)
the transistor goes into linear operation, which results in lower
transconductance nonlinearity
. However, the output
conductance nonlinearity
increases significantly above
due to the decreasing . The contribution due
to the cross-term remains relatively constant over a broad range
of
values.
Fig. 6 shows the IIP2 and IIP3 versus
of the resistively
loaded CS-stage. These graphs were derived from the Taylor
coefficients
, and using
IIP2
dB
IIP3
dB (17)