Journal Article•
Wire bonding strategies to meet thin packaging requirements. ii
About: This article is published in Solid State Technology.The article was published on 1993-03-01 and is currently open access. It has received 9 citations till now. The article focuses on the topics: Wire bonding & Integrated circuit packaging.
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15 Mar 1994
TL;DR: In this article, a low-cost, manufacturable process for stacking memory chips up to four-high on a multichip module (MCM) substrate is described, which typically enables large (2-4x) reductions in substrate cost for memory intensive designs, with only a small increment in assembly cost, thereby achieving lower total MCM cost and greater utilization of the high wiring density and good thermal conductivity of the MCM substrate.
Abstract: A new, low-cost, manufacturable process for stacking memory chips up to four-high on a multichip module (MCM) substrate is described. The process is particularly useful when utilized with a high-performance thin-film interconnection substrate ("MCM-D"), as the technique typically enables large (2-4x) reductions in substrate cost for memory-intensive designs, with only a small increment in assembly cost, thereby achieving lower total MCM cost, and greater utilization of the high wiring density and good thermal conductivity of the MCM substrate. The technology was developed and demonstrated using commercially available MCM assembly equipment (dicing, adhesive die attach, and wire bonding equipment). Fully functional memory modules incorporating 2-high stacks have been fabricated, and have passed basic thermal shock tests. >
31 citations
TL;DR: In this paper, a method using springs to simulate the condition of forces acting on a section of the bonding wire was proposed, where the coefficients of elasticity and plasticity of the springs were determined by the bending angle of two linkages which simulates the elastic-plastic deformation of the bond wires.
Abstract: Several wirebonding loops were proposed to prevent the necking in wire. Most of experimental statistical methods were applied in the analysis of wirebonding and it was time consuming and without the precise analysis. Further, the finite element analysis is the most powerful tool for stress analysis; however, it is too complex for analyzing a large deformation. Hence, this paper proposes a novel method using springs to simulate the condition of forces acting on a section of the bonding wire. The bonding wire profile can be formed by combining several sets of linkage with springs, wherein the coefficients of elasticity and plasticity of the springs are determined by the bending angle of two linkages which simulates the elastic-plastic deformation of the bonding wires. The operational model ran be simplified by using the multiple degrees of freedom of the linkages/springs to analyze the profile and forces of the bond wire. Experiments have been conducted to validate the model. Good agreement is obtained between analytical prediction and experimental data. Finally, three basic preforms for wirebonding are introduced, and it ran be seen that the loop sagging at the second bond is improved and the loop height can be controlled by proper design. Necking and fracture during the bonding process can be avoided by the present method and the optimum wire bonding profiles can also be achieved.
21 citations
TL;DR: In this article, the authors highlight the key issues facing the packaging of high-performance digital and rf electronics, including increased speed, the number of input/output interconnects, decreased pitch, and decreased cost.
Abstract: The trend for microelectronic devices has historically been, and will continue to be, toward a smaller feature size, faster speeds, more complexity, higher power, and lower cost. The driving force behind these advances has traditionally been microprocessors. With the tremendous growth of wireless telecommunications, rf applications are beginning to drive many areas of microelectronics that traditionally were led by developments in microprocessors. An increasingly dominant factor in rf microelectronics is electronic packaging, and the materials needed to create the package, because the package materials strongly affect the performance of the electronics. Many challenges remain for the packaging of microprocessors as well. These challenges include increased speed, the number of input/output interconnects, decreased pitch, and decreased cost. This article highlights the key issues facing the packaging of high-performance digital and rf electronics.
18 citations
TL;DR: In this paper, the authors proposed different profiles of a wirebond utilizing a linkage-spring model, and loop heights are minimized in order to prevent wire sweep during molding, and the design rules in the looping process are defined and four examples of triangle and T-profiles are also presented.
Abstract: Different profiles of a wirebond utilizing a linkage-spring model are proposed in this paper, and loop heights are minimized in order to prevent wire sweep during molding. To analyze loop profiles, a nonquantitative, time-consuming, experimental statistical method was applied in previous studies. Although the finite element model is the most powerful tool in stress analysis, it is more complex in analyzing a large deformation as compared to the linkage-spring model. The purpose of this paper is to simulate the capillary trajectory from the first bond to the second bond stages by a linkage-spring model developed by Lo, and then to discover the proper wirebond trajectories. To meet with the gold wire properties, the transient temperature distribution along the gold wire during the bonding process is considered, Accordingly, the spring constants in a linkage-spring model are modified along the wire. Furthermore, the design rules in the looping process are defined and four examples of triangle- and T-profiles of a wirebond are also presented.
18 citations
01 Jan 2006
TL;DR: A high-productivity, ultra-low loop, with <70µm loop height, is one example as mentioned in this paper, with new shapes being developed as new demands are identified.
Abstract: Stacked die, die-to-die, and multi-tiered package demand has driven the development of over 20 premium-process wire bond loop shapes. A high-productivity, ultra-low loop, with <70µm loop height, is one example. The array of loop shape solutions from which a packaging engineer can choose has grown substantially, with new shapes being developed as new demands are identified. Continuous wire bonding developments increase the process productivity, flexibility and versatility.
16 citations
Cites background from "Wire bonding strategies to meet thi..."
...The ability to shape a wire bond loop, with well-controlled bends and kinks, has been in continuous development for over 12 years [4], [5]....
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