scispace - formally typeset
Proceedings ArticleDOI

Zero Knowledge Authentication for Reuse of IPs in Reconfigurable Platforms

Reads0
Chats0
TLDR
This work proposes a zero knowledge authentication strategy for safe reusing of RIPs that relies on verification of proof of authentication (PoA) mark embedded in the RIP by the RIP producers, and experimental results validate the proposed mechanism.
Abstract
A key challenge of the embedded era is to ensure trust in reuse of intellectual properties (IPs), which facilitates reduction of design cost and meeting of stringent marketing deadlines. Determining source of the IPs or their authenticity is a key metric to facilitate safe reuse of IPs. Though physical unclonable functions solves this problem for application specific integrated circuit (ASIC) IPs, authentication strategies for reconfigurable IPs (RIPs) or IPs of reconfigurable hardware platforms like field programmable gate arrays (FPGAs) are still in their infancy. Existing authentication techniques for RIPs that relies on verification of proof of authentication (PoA) mark embedded in the RIP by the RIP producers, leak useful clues about the PoA mark. This results in replication and implantation of the PoA mark in fake RIPs. This not only causes loss to authorized second hand RIP users, but also poses risk to the reputation of the RIP producers. We propose a zero knowledge authentication strategy for safe reusing of RIPs. The PoA of an RIP producer is kept secret and verification is carried out based on traversal times from the initial point to several intermediate points of the embedded PoA when the RIPs configure an FPGA. Such delays are user specific and cannot be replicated as these depend on intrinsic properties of the base semiconductor material of the FPGA, which is unique and never same as that of another FPGA. Experimental results validate our proposed mechanism. High strength even for low overhead ISCAS benchmarks, considered as PoA for experimentation depict the prospects of our proposed methodology.

read more

References
More filters
Journal ArticleDOI

Fingerprinting techniques for field-programmable gate array intellectual property protection

TL;DR: This work presents the first technique that leverages the unique characteristics of field-programmable gate arrays (FPGAs) to protect commercial investment in intellectual property through fingerprinting.
Proceedings ArticleDOI

Signature hiding techniques for FPGA intellectual property protection

TL;DR: This work presents the first known attempt to leverage the unique characteristics of FPGAs to protect commercial investments in intellectual property through the application of a watermark.
Proceedings ArticleDOI

Robust FPGA intellectual property protection through multiple small watermarks

TL;DR: A method for watermarking field programmable gate array (FPGA) intellectual property (IP) that achieves robustness by responding to three specific weaknesses: complexity of copy detection, vulnerability to mark removal after revelation for ownership verification, and mark integrity issues due to partial mark removal.
Journal ArticleDOI

Power Signature Watermarking of IP Cores for FPGAs

TL;DR: This is the first watermarking method where the signature (watermark) is detected at the power supply pins of the FPGA, and a detection algorithm is introduced which can decode the signature from a voltage trace with high reliability.
Proceedings ArticleDOI

Zero overhead watermarking technique for FPGA designs

TL;DR: A new FPGA watermarking technique that guarantees zero design overhead is proposed and is demonstrated by applying the proposed technique on several real-life FPGAs, which range in size from a few thousand to more than two million gates, on Xilinx devices.
Related Papers (5)