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How do they make 7 nm transistors? 

AND gate
Node (circuits)
Logic gate
Threshold voltage
Schottky diode

Answers from top 8 papers

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Papers (8)Insight
Proceedings Article•DOI
Process Optimization of Perpendicular Magnetic Tunnel Junction Arrays for Last-Level Cache beyond 7 nm Node
Lin Xue, C. Ching, A. Kontos, Jaesoo Ahn, Wang Xiaodong, Renu Whig, Hsin-Wei Tseng, James Howarth, S. Hassan, H. Chen, Mangesh Bangar, Liang Shurong, Wang Rongjun, Mahendra Pakala 
18 Jun 2018
14 Citations
The device performance along with the process capability to make MTJ array at 88 nm pitch provides opportunities for LLC applications.
Open access•Journal Article•DOI
Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs
Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Rock-Hyun Baek 
17 Aug 2018-IEEE Journal of the Electron Devices Society
56 Citations
In spite of that, sub-7-nm node NSFETs attain better RC delay than sub-7-nm node as well as 10-nm node FinFETs for standard and high performance applications, showing better chance for scaling down to sub-7-nm node and beyond.
Journal Article•DOI
Sub-10 nanometre fabrication: molecular templating, electron-beam sculpting and crystallization of metallic nanowires
Mikas Remeika, Alexey Bezryadin 
17 May 2005-Nanotechnology
44 Citations
single-electron tunnelling transistors, with dimensions below 10 nm, possibly operating at room temperature.
Journal Article•DOI
An optimized design of 10-nm-scale dual-material surrounded gate MOSFETs for digital circuit applications
Fayçal Djeffal, N. Lakhdar, A. Yousfi 
01 Oct 2011-Physica E-low-dimensional Systems & Nanostructures
35 Citations
These characteristics make the optimized 10-nm transistors potentially suitable for deep nanoscale logic and memory applications.
Journal Article•DOI
Design of 10-nm-scale recessed asymmetric Schottky barrier MOSFETs
Yaohui Zhang, Jun Wan, Kang L. Wang, Bich-Yen Nguyen 
07 Aug 2002-IEEE Electron Device Letters
31 Citations
These characteristics make the 10-nm or even sub-10 nm transistors potentially suitable for logic and memory applications.
Journal Article•DOI
Effects of annealing on top-gated MoS2 transistors with HfO2 dielectric
Peng Zhao, Angelica Azcatl, Pavel Bolshakov, Jiyoung Moon, Christopher L. Hinkle, Paul K. Hurley, Robert M. Wallace, Chadwin D. Young 
19 Jan 2017-Journal of Vacuum Science & Technology. B. Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena
31 Citations
This work demonstrates how the fabrication process can affect the yield and the electrical characterization of top-gated TMD transistors, which in...
Journal Article•DOI
Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node
Jun-Sik Yoon, Eui-Young Jeong, Chang-Ki Baek, Ye-Ram Kim, Jae-Ho Hong, Jeong-Soo Lee, Rock-Hyun Baek, Yoon-Ha Jeong 
05 Aug 2015-IEEE Electron Device Letters
30 Citations
Using systematic TCAD-based RC calculation, we suggest optimized overlap/underlap lengths in the 7-nm node FinFETs to overcome the scaling limitations.
Journal Article•DOI
High gain SiGe heterojunction bipolar transistors grown by rapid thermal chemical vapor deposition
Martin L. Green, D. Brasen, H. Temkin, R. D. Yadvish, T. Boone, Leonard C. Feldman, M. Geva, B. E. Spear 
01 Jan 1990-Thin Solid Films
17 Citations
These HJBTs show great promise as microwave transistors.

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