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These transistors show a positive temperature coefficient in the on-resistance characteristics, which will enable easy paralleling of the devices.
It is in a reasonable agreement with the experiments for both n-channel transistors and silicon on sapphire sample.
In this paper, we present a new and efficient switched-current memory cell consisting of six MOS transistors.
Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries.
The results demonstrate a new scheme of building nanometer-scale transistors.
Proceedings ArticleDOI
H. Bakoglu, J. Meindl 
01 Jan 1987
38 Citations
Predictions indicate that in ten years a 0.7μm CMOS micro-processor with 6-million transistors will execute 30-60 MIPS.
Journal ArticleDOI
51 Citations
These are the fastest silicon transistors reported to date in terms of both fT and fmax figures.
The parameter variations are random in nature and are expected to be more pronounced in minimum geometry transistors commonly used in memories such as SRAM.
A new cell composed of a pair of adjacent gates provides high utilization of input transistors.
Consequently, their design is important for a good thermal behavior and reliability of the transistors.
Proceedings ArticleDOI
R. Heald, P. Wang 
07 Nov 2004
131 Citations
Hence, the small transistors in SRAM cells are particularly sensitive to these variations.
Journal ArticleDOI
Erez Braun, Kinneret Keren 
93 Citations
We show that it can lead all the way from DNA molecules to working transistors in a test-tube.
The transistors are scalable because of the thin silicon technology and the memories are highly scalable because they allow efficient coupling between the carriers and storage region.
These transistors can allow unique design flexibility; for example, a NAND gate can be achieved in a uniformly doped nanowire with four contacts.
Our findings paint a picture of BTI and TDDB that in many respects is similar to that of Si transistors but with some unique characteristics.
Our conclusions are further supported by measuring all currents in the three-terminal configuration of the transistors before and during the breakdown and by using a drain current injection technique.
Journal ArticleDOI
Qin Zhang, Wei Zhao, Alan Seabaugh 
555 Citations
This formula is consistent with two recent reports of interband tunnel transistors, which show lower than 60-mV/dec subthreshold swings and provides two simple design principles for configuring these transistors.

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