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How many transistors are present in D latch? 

Equivalent circuit
CMOS
Power (physics)
Spice
Flip-flop

Answers from top 9 papers

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Papers (9)Insight
Open access•Journal Article•DOI
MCML D-Latch Using Triple-Tail Cells: Analysis and Design
Kirti Gupta, Neeta Pandey, Maneesha Gupta 
04 Nov 2013-Active and Passive Electronic Components
23 Citations
The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch.
Proceedings Article•DOI
Low power D-latch design using MCML tri-state buffers
Radhika, Neeta Pandey, Kirti Gupta, Maneesha Gupta 
24 Mar 2014
14 Citations
The proposed D-latch consumes less power as it makes use of low power tri-state buffers which promotes power saving due to reduction in the overall current flow in the circuit during the high impedance state.
Journal Article•DOI
Turn-Off Time as an Early Indicator of Insulated Gate Bipolar Transistor Latch-up
Douglas W. Brown, Manzar Abbas, Antonio Ginart, Irfan N. Ali, P.W. Kalgren, George Vachtsevanos 
01 Feb 2012-IEEE Transactions on Power Electronics
101 Citations
Experimental results demonstrated the feasibility of using the proposed metric as a precursor to transistor latch-up.
Journal Article•DOI
Novel D Latches and D Flip-Flops with Set and Reset Ability in QCA Nanotechnology Using Minimum Cells and Area
Mojtaba Gholamnia Roshan, Mohammad Gholami 
03 Aug 2018-International Journal of Theoretical Physics
32 Citations
Therefore, considering the importance of D Flip-Flops among different types of Flip-Flops and their more efficient performance, this paper presents new structures for D Latch and D Flip-Flops in QCA nanotechnology.
Journal Article•DOI
A better understanding of CMOS latch-up
G.J. Hu
01 Jan 1984-IEEE Transactions on Electron Devices
85 Citations
The equivalent circuit model offers a simple view on latch-up, while 2-D modeling provides more physics and quantitative understanding of latch-up.
Proceedings Article•DOI
High-performance low-power magnetic tunnel junction based non-volatile flip-flop
Taehui Na, Kyungho Ryu, Jisu Kim, Seong-Ook Jung, Jung Pill Kim, Seung-Hyuk Kang 
01 Jun 2014
16 Citations
The separated latch and sensing circuit structure maximizes the performance of latch operation, minimizes power consumption, and improves MTJ lifetime.
Proceedings Article•DOI
Design and performance evaluation of a low cost Full Protected CMOS Latch
Saeideh Shirinzadeh, Rahebeh Niaraki Asli 
01 Oct 2013
8 Citations
This paper proposes an efficient robust latch design in 45 nm CMOS technology.
Journal Article•DOI
Precise final state determination of mismatched CMOS latches
W.A.M. Van Noije, Wentai Liu, S.J. Navarro 
01 May 1995-IEEE Journal of Solid-state Circuits
20 Citations
From this study we show that the final state depends on both initial voltages and latch mismatches.
Journal Article•DOI
Multiple Node Upset-Tolerant Latch Design
Xin Liu
23 Apr 2019-IEEE Transactions on Device and Materials Reliability
25 Citations
The DNU-tolerant latch, DNUTL-1, demonstrates considerable advantages in terms of the area, propagation delay, power, and the delay-power-area product.

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