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This paper presents an improvement in our previous methodology to generate efficient transistor networks.
In this paper, we propose a structure that improves the OFF state and switching behavior of the transistor without increase in the transistor length.
In this paper, we propose a novel transistor-level optimization method.
The technique can be coupled with transistor sizing to achieve the desired improvement in circuit delay.
Results indicate that the spacer thickness significantly affects the performance of the transistor.
Reducing the fringing capacitance is shown to be the most effective approach to meet the required transistor delay.
Proceedings ArticleDOI
Pablo Aguirre, Fernando Silveira 
28 Aug 2006
13 Citations
By taking advantage of a compact MOS transistor model, we show how the circuit can be easily designed to precisely fix the drain voltage of the cascoded transistor just above its saturation voltage.
We have demonstrated the first bipolar magnetic junction transistor using a dilute magnetic semiconductor.
Measured transistor values show excellent potential for both power and low-noise amplification applications.
The current gain degradation appears to be predominantly due to displacement damage in the bulk of the transistor.

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