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We demonstrate the usefulness of the proposed technique to evaluate a built-in-test technique for a radio frequency low noise amplifier and to set test limits that result in a desired tradeoff between test metrics.
Proceedings ArticleDOI
N.R. Sharma, Lok Teng Kee 
22 Oct 2007
1 Citations
Result shows that with this test methodology for high density and capacity of RF Power Amplifier testing, test system cost is significantly reduced without the expense of sacrificing the accuracy of measurements.
A more accurate method for generating and evaluating MOS circuit test patterns is to work from the switch-level representation of the circuit under test, testing for transistor stuck-on and stuck-open faults.< >
This result shows that doping profiles measured on a uniformly doped test wafer may be quite different from the doping profile in the active base of a fine geometry microwave transistor.
Experimental results on several circuits confirm the high accuracy of our variance analysis technique and show a nearly 72% reduction in the number of tests for a three-stage amplifier circuit in the experiment after the application of the test selection algorithm.
The method is particularly suitable for compact modeling and technology characterization from high-frequency transistor test structures with no separate substrate contacts.
Experimental results obtained for a silicon RF bipolar transistor demonstrate validity of the method.
The tool has proven to bevery useful in the early evaluation of test strategies, providing similarresults to those obtained at the transistor-level.

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