Showing papers on "40-bit encryption published in 1991"

Encryption synchronization combined with encryption key identification

Abstract: In an encrypted radio system, transmsitters and receivers can each be provided with a plurality of encryption algorithms (407 and 425) and/or encryption key variables (408 and 426). A unique logical ID (409 and 427) corresponds to each of the above. During transmission of an encrypted message, both encryption synchronization information (319) and information concerning the logical ID (318) is repetitively interleaved with the encrypted message itself. So configured, a receiver that temporarily loses viable reception can again obtain encryption synchronization and algorithm/key information, and therefore rapidly recover from the reception disturbance.

A cryptosystem for cellular telephony

Abstract: A relatively secure, self-inverting, symmetric key cryptosystem designed for efficient implementation on an 8-bit microcomputer. The cryptosystem is especially well suited use in cellular telephony. The method of encryption is comprised of three stages: 1) an autokeyed encryption, 2) the use of a one-time pad encryption where the key is derived from a portion of the message as encrypted by the first stage, and 3) a second autokeyed decryption that is the inverse of the first.

Automatic encryption selector

Abstract: A radio (100) capable of automatically selecting an encryption algorithm from among a plurality of algorithms (122 and 124) is disclosed. The method for automatically selecting the proper encryption hybrid includes the steps of: attempting to decrypt the encrypted signal with one of the plurality of encryption algorithms; determining if the encryption algorithm used to decrypt the encrypted signal matches the encryption algorithm used by the encrypted signal; and developing a control signal upon the proper matching of the encryption algorithms.

Facsimile message encryption system

Abstract: A system for maintaining the security of information transmitted between facsimile machines includes a transmitting/receiving facsimile machine for receiving input sheets having an encryption zone; an image sensor for detecting the encryption zones; an encryption device for scrambling messages that appear within an encryption zone. Further the system includes means for sensing encryption zones on transmitted messages and for decoding messages that have been scrambled within the encryption zones.

Method for recovering from encryption key variable loss

Abstract: A method for recovering from encryption key variable loss, either inadvertent or the result of tampering. A predetermined key encryption key is encrypted with itself at the time when keys are first loaded, and the resultant key loss key is stored in non-volatile memory. This key loss key acts as a key encryption key for decryption of new shadow and traffic keys.

Method and apparatus for encryption/decryption of digital multisound in television

Abstract: The present invention relates to methods and apparatus for encryption and decryption, respectively, of digital sound in television. The decryption takes place in two steps. The first step, encryption with running key, is achieved by adding modulo 2 a pseudo random sequence to the digital signal containing a sound information. The pseudo random sequence is preferably generated by a non-linear feedback register initialized by the control word. The second step involves encryption of the control word, thereby being transmitted to the receiver in ciphered form. The encryption is preferably achieved by a microprocessor also performing coding of the control word for forward error correction. The control word in turn is generated by a true random sequence generator. The invention enables an encryption that is secure against breaking without deteriorating the sound quality and also enables efficient handling of the key of the encryption.

Key management in encryption systems

Abstract: A key management system for encryption keys removes the effect of secure communications loss during a rekey period in a secure communications system Use of key indexes to partition encryption keys into usable subgroups such that during a rekey period, continuous secure communications are maintained throughout the entire secure communications system

VLSI implementation of a new block cipher

Abstract: The high speed architecture for a VLSI implementation of a new smart-key block cipher is presented. The chip performs data encryption and decryption in a single hardware unit. It runs with a maximum clock frequency of 33 MHz permitting a data conversion rate of more than 55 Mb/s. This high data rate, compared to currently available DES (data encryption standard) implementations, has been achieved by implementing a pipelined architecture and by using a sophisticated data scheduling scheme guaranteeing a continuously fully loaded pipeline. >

Data encryption device and method for data encryption

Abstract: An encryption method is taught which chooses certain bytes of data, stored in a particular on-chip memory, as encryption keys. These chosen bytes are used to encrypt themselves, and all of the remaining data in the above mentioned particular memory. The chosen bytes do not have values specifically assigned for encryption, they are merely chosen, according to a rule, from the body of data to be encrypted. When this technique is implemented, each byte of data, stored in the mentioned memory, is combined (for example using an exclusive NOR gate) with one of the designated encryption key bytes prior to disclosure. The user is not required to provide, program, or safeguard a set of key bytes separately. Additionally, no silicon area is wasted in storing such bytes. An intruder would need certain pieces of the original data in order to decipher the results of this encryption technique. Additionally, this technique degrades gracefully. The keys are chosen such that encrypted data does not have a single common dependency. Thus, in the event a single key is discovered, only a very small portion of the encrypted data will be disclosed.

Multiplication as Parallel as Possible

Abstract: Public key encryption/decryption with modulus arithmetic is used in a variety of cryptographic applications. A tough computational problem arises due to the very long integer arithmetic needed. Usually serial-parallel multiplication is employed, which slows down speed to the order of k=log2(n), where n is the modulus. This paper describes a possible implementation of a method using parallel multiplication schemes at the order of log(k) in combination with incomplete modulus reduction. As many partial products as possible are implemented in parallel (As Parallel As Possible, APAP). This leads to a mixture of linear and logarithmic time complexity. This paper describes a hardware solution for the APAP-multiplier with optimized dynamic adder cells without storage elements. Additional available silicon area can be traded against speedup in a smooth way. The underlying method is described and proved in [Posch90]. Using 664 bit long operands, a 40mm2 chip manufactured in 1.2 micron CMOS technology can reach an RSA encryption/decryption rate of 240 kbits/second.