Showing papers on "Adaptive Multi-Rate audio codec published in 1980"

A modified adaptive transform coding scheme with post-processing-enhancement

Abstract: The purpose of this paper is to describe a scheme for low-bit-rate transmission of speech. The scheme consists of a cascade of a codec with a post-processor. The codec is based on a modified version of the LPC Vocoder Driven Adaptive Transform Coding algorithm. The Post-Processor performs a short-time Fourier analysis/synthesis at the receiver output and, by exploring the known structure of the quantization noise introduced by the codec, it is capable of speech enhancement. The performance of this scheme will be demonstrated at 9.6 kb/s and at 7.2 kb/s.

Digital Encoding of Phase Shift Keying Voiceband Data Signals

Abstract: Computer simulation was used to evaluate the performance of eleven coder/decoders (CODEC's) with phase shift keying (PSK) and differential PSK(DPSK) voiceband data signals. The CODEC's were PCM, differential PCM and delta modulation systems designed for speech and operating at bit rates from 16 to 64 kbits/s. The voiceband data signals processed by these CODEC's were demodulated to determine the phase error caused by the CODEC. The phase error introduced by the CODEC's is a function of the phase of the CODEC sampling clock relative to the data modem bit clock. Some of the statistics of the phase error are presented. Three performance metrics were used to evaluate the performance of these CODEC's-signal to quantizing noise ratio, variance of the phase error and maximum value of the phase error.

A Single-Chip Speech Synthesizer for the PARCOR CODEC : A-4: LSI DEVICES

Abstract: A speech synthesizer for PARCOR CODEC, using 2 µm E/D n-MOS microfabrication technology, is developed. The synthesis operation is executed through a multistage lattice filter which is organized by RAM, adder/substracter, and multiplier. The number of the filter stage can be altered to either 8 or 10 by an external signal, according to the demanded quality. The synthesis operation is fully controlled by the program stored in the ROM. Input signals of the synthesizer are the sound source parameter and PARCOR coefficients, and have a fixed point 2's complement format. Internal data bit length is 16 bits. The parallel multiplier used in the synthesizer achieves high speed operation and integration density using modified Booth's algorithm and cellular array formation. The measured maximum clock frequency and power dissipation of the synthesizer are 5 MHz and 450 mW, respectively.