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Adaptive Multi-Rate audio codec

About: Adaptive Multi-Rate audio codec is a research topic. Over the lifetime, 1467 publications have been published within this topic receiving 19736 citations. The topic is also known as: AMR & Adaptive Multi-Rate.


Papers
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Proceedings Article
01 Jan 1999
TL;DR: Simulation results show that the new algorithm achieves substantial gains over separate error correction with hard decisions prior to source decoding and classical techniques for error detection and bad frame handling as widely used in the present mobile-radio systems.
Abstract: A new algorithm called Channel-Coded Optimal Estimation (CCOE) is adapted to a CELP speech codec. The CCOE-algorithm performs joint source-channel decoding by optimal estimation using bit-reliability informations (soft-bits) and source statistics. The basic algorithm for a simple transmission scenario with a single scalar quantizer has been recently stated by the author. In this paper the basic idea is extended for the use in a CELP speech-codec that was developed for enhanced speech transmission in the GSM mobile radio channel. Simulation results based on informal listening tests are given which show that the new algorithm achieves substantial gains over separate error correction with hard decisions prior to source decoding and classical techniques for error detection and bad frame handling as widely used in the present mobile-radio systems.

3 citations

Journal ArticleDOI
TL;DR: A newly developed single-board video codec using Video Image Signal Processors (VISPs) that has both a CCITT H.261 mode and a proprietary mode is discussed.

3 citations

Proceedings ArticleDOI
03 Dec 2003
TL;DR: This paper proposes a 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems, and demonstrates its flexibility and usefulness.
Abstract: This paper proposes a 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems, and demonstrates its flexibility and usefulness. This architecture consists of a half-duplex 720/30P encoding core, a half-duplex 1080I decoding core, an audio DSP, a RISC, and a multiplexer/de-multiplexer core with a dual-memory scheme for supplying data at high speeds. The LSI, which integrates 3.8 million transistors on a 9.7 mm/spl times/9.7 mm die using the 0.13 /spl mu/m seven-metal CMOS process, implements 720/30P encoding with 1.1 W, 1080I decoding with 0.8 W, and full-duplex 480P encoding and decoding simultaneously with 1.4 W. This LSI will make it possible for consumers to use HDTV quality equipment on a more widespread scale.

3 citations

Proceedings ArticleDOI
27 Aug 2007
TL;DR: It is shown that the only one domain where a performance gain can be achieved from the linear interpolation procedure is in the Line Spectral Frequencies (LSF) domain, which is the best domain to perform features interpolation in Distributed Speech Recognition systems.
Abstract: In this paper, we examine the best domain to perform features interpolation in Distributed Speech Recognition (DSR) systems. We show that the only one domain where a performance gain can be achieved from the linear interpolation procedure is in the Line Spectral Frequencies (LSF) domain. A DSR scenario where the ITU-T G.723.1 codec is employed is also investigated. The recognition feature generated from the reconstructed speech is highly sensitive to the encoding noise. We have also shown that the LSF quantization scheme used by the G.723.1 codec decreases the recognition performance by approximately 2 %.

3 citations

Journal ArticleDOI
TL;DR: An implementation of a CCITT G.721 compatible 32kbit/s ADPCM codec, using a general-purpose digital signal processor FDSP-3 (MB8764), and it is shown that the whole codec computation can be accomplished in about 2350 machine cycles.
Abstract: This paper describes an implementation of a CCITT G.721 compatible 32kbit/s ADPCM codec, using a general-purpose digital signal processor FDSP-3 (MB8764). A single-channel ADPCM codec is realized by two FDSP-3 chips-one for the encoder and the other for the decoder. Meticulous programming techniques are employed to achieve exact computation of the CCITT algorithm exploiting all the available resources of the 16-bit fixed-point DSP. It is shown that the whole codec computation can be accomplished in about 2350 machine cycles. Thus, two FDSP-3 chips operating at 10 MHz machine cycle can handle the whole computation. The paper also covers the comparison of straight fixed-point format and the G.721 realization, and briefly examines the compatibility issue between these two methods.

3 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202310
202214
20201
20193
20183
201721