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Showing papers on "Adder published in 1974"


Journal ArticleDOI
TL;DR: In this article, an implementation scheme for the operations of addition and subtraction in the residue number system is described, which is based on the property that the set of residues modulo m form a finite group under addition and subtractions (modulo m).
Abstract: This correspondence describes an implementation scheme for the operations of addition and subtraction in the residue number systems. The method is based on the property that the set of residues modulo m form a finite group under addition and subtraction (modulo m). The proposed adder/subtractor structure is very systematic and, hence, suitable for MSI/LSI realization.

34 citations


Journal ArticleDOI
D. Herrell1
TL;DR: The design of a one-bit full adder circuit based on a family of simple Josephson logic gates is considered and was found to operate, even with the large devices used, with an add time far superior to existing semiconductor adder circuits.
Abstract: The design of a one-bit full adder circuit based on a family of simple Josephson logic gates is considered. The adder circuit was fabricated using a 25μm minimum linewidth technology and was found to operate, even with the large devices used, with an add time far superior to existing semiconductor adder circuits.

32 citations


Patent
Giraudon Claude1
23 Jan 1974
TL;DR: In this paper, a self-adapting anti-jamming device having (n + 1) sensors and enabling the restituting of the signal emitted by a source in the presence of n punctiform noise sources, comprising a combination assembly having an adder and n subtractors, an orthonormalization assembly comprising n AGC circuits, n (n - 1)/2! subtractors each combined with a correlation module, an intercorrelation set comprising n correlation modules, an adders and a subtractor.
Abstract: Self-adapting anti-jamming device having (n + 1) sensors and enabling the restituting of the signal emitted by a source in the presence of n punctiform noise sources, comprising a combination assembly having an adder and n subtractors, an orthonormalization assembly comprising n AGC circuits, n (n - 1)/2! subtractors each combined with a correlation module, an intercorrelation set comprising n correlation modules, an adder and a subtractor.

29 citations


Patent
18 Jun 1974
TL;DR: A digital indication exposure meter includes a photoelectric transducer circuit which produces an output current proportional to the intensity of lights incident to a photo-electric element, including a circuit wherein an integrating capacitor is charged up by a photo electric current of the photoelectric element in a manner that the voltage across both ends of the capacitor is proportional to a logarithm of the quantity of light received during a time of light measuring as mentioned in this paper.
Abstract: A digital indication exposure meter includes a photoelectric transducer circuit which produces an output current proportional to the intensity of lights incident to a photoelectric element, said transducer circuit including a circuit wherein an integrating capacitor is charged up by a photoelectric current of the photoelectric element in a manner that the voltage across both ends of the capacitor is proportional to the logarithm of the quantity of light received during a time of light measuring, a timer circuit which produces electric signals corresponding to the time of light measuring, an analog-digital converter which converts the analog output signal of the voltage in the integrating capacitor into a digital form and retains the information in a digital form, a coding circuit which is set to produce digital signals corresponding to film sensitivity, an adder circuit which computes the digital output of the analogdigital converter together with the digital information from the coding circuit, a decoder for converting the digital output from the adder into another digital output suitable for numeral displaying, and numeral displaying devices for indicating the output of the decoder.

28 citations


Journal ArticleDOI
TL;DR: A circuit is described in which the error produced by overflow is delayed and fed back into the filter and it is shown that this circuit improves the overflow behaviour.
Abstract: In digital filters, nonlinear phenomena caused by adder overflow can occur. Some of these phenomena that have been observed in a 2nd-order recursive digital filter are mentioned. A circuit is described in which the error produced by overflow is delayed and fed back into the filter. It is shown that this circuit improves the overflow behaviour.

22 citations


Patent
01 Apr 1974
TL;DR: In this paper, an array of 3-bit adders is constructed from a combination of threshold logic modules, and the resulting simplifications permit circuit realization in the form of an array.
Abstract: Apparatus and methods for performing the parallel m-bit by n-bit multiplication of two binary 2's complement numbers by converting the multiplication process to an equivalent parallel array addition in which the operands are positive partial products including (1) terms formed by ANDing a multiplier bit (or its complement), and (2) a multiplicand bit (or its complement) and five additional partial product terms. The resulting simplifications permit circuit realization in the form of an array of 3-bit adders each formed from a combination of threshold logic modules.

21 citations


Journal ArticleDOI
S. Lee1, Hsu Chang1
TL;DR: It is important to point out that only the symmetric switching function devices offer rewrite-ability to eliminate the part number problem, and accommodation for a large number of inputs to ease interconnection and delay equalization problems.
Abstract: Although the literature on the bubble logic devices is limited, the concepts and device configurations are diverse. In conductor-access devices, logic can be performed by bubble transfer operations. In field-access devices, logic can be performed by providing alternative paths which are selected by interaction between bubbles. Examples include the conjugate logic gates, the resident-bubble cellular logic, and the chevron 3-3 circuits. Logic can also be performed by counting bubbles, such as in the symmetric switching function implementation. The various mechanisms for implementing bubble logic are all described by truth tables. To assess their efficiency, they are compared in terms of space and delay when they are used to implement the same logic element - a full adder. They are all comparable except for the resident-bubble cellular logic which requires excessive space and delay. However, it is important to point out that only the symmetric switching function devices offer rewrite-ability to eliminate the part number problem, and accommodation for a large number of inputs to ease interconnection and delay equalization problems.

21 citations


Patent
11 Feb 1974
TL;DR: McIver and McIver as discussed by the authors employed non-threshold logic to form a full adder at each one of its computational nodes, which was made up of a combination of pnp multiple emitter transistors in emitter follower configuration forming eight AND gates coupled to a combination npn multiple EMIT transistors and four OR gates.
Abstract: HIGH DENSITY MULTIPLIER George W. McIver James L. Buie ABSTRACT OF THE DISCLOSURE A sequential-add multiplier possessing high operating speed and high packing density in integrated form employs non-threshold logic to form a full adder at each one of its computational nodes. The full adder is made up of a combination of pnp multiple emitter transistors in emitter follower configuration forming eight AND gates coupled to a combination of npn multiple emitter transistors in emitter follower configuration forming four OR gates.

21 citations


Patent
26 Nov 1974
TL;DR: In this article, a greatly simplified calculator circuit implemented using I2L technology is fabricated on a relatively small semiconductor chip resulting in high yield, and a unique feature of such calculator which permits direct or indirect addressing while reducing the number of ROM instructions required and hence the size of the ROM to permit fabrication on the smaller chip is embodied in the present invention.
Abstract: A greatly simplified calculator circuit implemented, for example, utilizing I2 L technology, is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator which permits direct or indirect addressing while reducing the number of ROM instructions required and hence the size of the ROM to permit fabrication on the smaller chip is embodied in the present invention. All memory instructions contain an address select bit to choose either the address contained in the ROM instruction word or the contents of the RAM address register which is loaded from the adder output. The RAM address register contents are incremented or added to by the adder to provide indirect addressing of the RAM while the ROM instruction word provides direct addressing of the RAM.

20 citations


Patent
Jean Rabasse1
02 Jan 1974
TL;DR: In this paper, a series type adder receiving numbers having different polarities is defined, characterized by means for calculating the sum S of the sign bits of the negative input numbers and effecting the storing thereof in a memory, means for extracting the exceeding number D appearing at the end of the calculating of Σ, and means for comparing S and D in order to determine the sign of a given number existing in memory register and to control the transferring thereof in true form in an output, preceded by its sign.
Abstract: Series type adder receiving numbers having different polarities, constituted by elementary series type adders combining the positive input numbers and the true complements of the negative input numbers to work out the sum Σ thereof, characterized in that it comprises means for calculating the sum S of the sign bits of the negative input numbers and effecting the storing thereof in a memory, means for extracting the exceeding number D appearing at the end of the calculating of Σ, means for comparing S and D in order to determine the sign of Σ existing in a memory register and in order to control the transferring thereof in true form, in an output, preceded by its sign.

19 citations


Patent
08 Mar 1974
TL;DR: In this article, a C-MOS transmission gate is provided in each stage with its input and output directly connected to the carry in and carry out leads of the stage, and the gate is switched by complementary control bits derived by stage input logic operating on the bits to be summed.
Abstract: In a binary parallel complementing L.S.I. adder, a C-MOS transmission gate is provided in each stage with its input and output directly connected to the carry in and carry out leads of the stage. The gate is switched by complementary control bits derived by stage input logic operating on the bits to be summed, whereby very fast passage of a carry through the stages is achieved. The transmission gate consists of p- and n- channel MOS transistors with their sources connected in common to the input and their drain electrodes likewise connected in common to the output.

Patent
21 Aug 1974
TL;DR: In this article, the serial adder serially forwards the sum of the addends into a sum register having delayed outputs which separately return the addend sum to each of the input registers.
Abstract: Input registers receive multiple binary addends and simultaneously forward them into a single serial adder where like binary digits are added starting with the least significant digit. For multiplication, the serial adder serially forwards the sum of the addends into a sum register having delayed outputs which separately return the addend sum to each of the input registers. Each returned sum is weighted a predetermined amount by delaying it with respect to the other sums. Because the numbers are binary, a delay of one digit place doubles the returned sum, and an advance of one digit place divides the returned sum in half. The delay outputs are weighted by powers of two, i.e., 1/8 , 1/4 , 1/2 , 1, 2, 4 depending on how many digit places are shifted in each return. The value of the multiplier is equal to the cumulative weights of the passed returns. A multiplier of 3/4 is established by passing the 1/2 and 1/4 returns and inhibiting the remainder. The weighted addend sums in the 1/2 and 1/4 return are loaded into the input registers, summed by the serial adder, and shifted into an output product register.

Journal ArticleDOI
TL;DR: Optimal networks with thirty different types of restrictions are listed for the one-bit fuli adder to ensure the minimization of the number of gates under different restrictions.
Abstract: Optimal networks with thirty different types of restrictions are listed for the one-bit fuli adder. Optimality is derined as the minimization of the number of gates under different restrictions.

Patent
12 Nov 1974
TL;DR: In this paper, sound carrier signals were combined with composite video signals to form the modulating signal input to the picture carrier frequency modulator, and the sum was clipped to develop a recording signal input for an electron beam disc recorder.
Abstract: Frequency modulated sound carrier waves and frequency modulated picture carrier waves are combined in an adder, and the sum is clipped to develop a recording signal input for an electron beam disc recorder. To reduce possible sound carrier interference in pictures reproduced from signals recovered during disc playback, sound carrier waves, in quadrature phase relation to those applied to the adder, are combined with composite video signals to form the modulating signal input to the picture carrier frequency modulator.

Patent
16 Aug 1974
TL;DR: A measuring device for a ring comprising a linear variable differential transformer mounted on a pin gauge for providing a voltage proportional to ring dimension is described in this paper, where a compensation circuit comprised of two thermistors is used for correcting dimensional error due to the difference in temperature of the ring and the pin gauge.
Abstract: A measuring device for a ring comprising a linear variable differential transformer mounted on a pin gauge for providing a voltage proportional to ring dimension A compensation circuit comprised of two thermistors is used for correcting dimensional error due to the difference in temperature of the ring and the pin gauge Each thermistor provides an output voltage which is combined in a first adder and the output of the first added and the voltage output of the differential transformer are combined in a second adder to provide an output proportional to ring diameter and corrected for temperature difference

Patent
Aage Pettersen1
22 Mar 1974
TL;DR: In this article, the pH measurement voltage from the pH electrode is converted to a binary coded digital signal and the digital signal from the thumb wheel switch is applied to the binary adder which produces a multiple bit output representing the difference.
Abstract: In a pH measuring instrument, automatic calibration (sloping) is performed by placing the pH electrode in a standard solution, dialing the pH of this standard solution into a decade thumb wheel switch, and depressing the slope switch. The measurement voltage from the electrode is converted to a binary coded digital signal. This signal and the digital signal from the thumb wheel switch are applied to a binary adder which produces a multiple bit output representing the difference. Clock pulses are supplied to a reversible digital counter which counts in a direction specified by the most significant bit of the binary adder output. The count in the reversible counter, representing the error, is converted to an analog signal which is used to control the reference voltage in a ratio system to produce a calibrated reading. The supply of clock pulses to the counter is automatically stopped when the error is zero.

Patent
23 Sep 1974
TL;DR: In this paper, a digital scaler adjusts the processing of an input signal to a digital fback integrator by a multiplying technique which is implemented by shifting the connections between an analog-to-digital converter and the input to an adder, both forming the input section of a digital feedback integrator, in order to maintain a constant dynamic range of the output signal.
Abstract: A digital scaler adjusts the processing of an input signal to a digital fback integrator by a multiplying technique which is implemented by shifting the connections between an analog-to-digital converter and the input to an adder, both forming the input section of a digital feedback integrator, in order to maintain a constant dynamic range of the output signal.

Journal ArticleDOI
TL;DR: A carry-look-ahead negabinary adder is proposed in the letter and it is shown that these adders make the design of a fast Negabinary multiplier feasible.
Abstract: A carry-look-ahead negabinary adder is proposed in the letter. It is shown that these adders make the design of a fast negabinary multiplier feasible.

Patent
Ming H. Louie1
30 Sep 1974
TL;DR: In this article, the correctness of half-sum, full-sum and look-ahead carry of a two-operand adder is checked using logic for checking the correctness.
Abstract: Logic for checking the correctness of half-sum, full-sum (or result) and look-ahead carry of a two-operand adder. Parity for half-sum or full-sum is first predicted and the predicted parity is then compared with the generated parity. The latter operation detects an error which has occurred during an arithmetic or logical operation in the adder. The digit look-ahead carry is compared with the generated digit carry for refining error isolation when an error is detected.

Patent
16 Jan 1974
TL;DR: In this paper, a 4 × 4 multiplier using four-bit threshold logic type adders is described, and the multiplier per se is arranged in a carry save configuration with first level pseudo type carry-look ahead with the highest weight bit of the product being accomplished by a wired OR connection.
Abstract: A 4 × 4 multiplier uses four bit threshold logic type adders. The multiplier per se is arranged in a carry save configuration with first level pseudo type carry-look ahead with the highest weight bit of the product being accomplished by a wired OR connection. The four bit adder itself provides two double threshold detectors responsive to logic levels provided by a level shifter which shifts the logical voltage levels produced by a differential amplifier which sums the four inputs of the adder circuit. This provides the sum output; an additional double threshold detector provides the first carry output and a typical threshold AND gate the second carry output.

Patent
10 Oct 1974
TL;DR: In this paper, a battery-powered hand-held calculator employs MOS/LSI circuits to perform arithmetic and financial calculations using a keyboard having a shift key to double the functions of selected keys.
Abstract: A battery-powered, hand-held, calculator employs MOS/LSI calculator circuits to perform arithmetic and financial calculations. Data and commands are input to the calculator from a keyboard having shift key to double the functions of selected keys. A 15-digit, seven-segment light emitting diode (LED) display serves as the output for the calculator. The calculator circuits include a read-only memory circuit in which the algorithms for performing the arithmetic and financial calculations are stored; a control and timing circuit for scanning the keyboard, retaining status information about the condition of the calculator or of an algorithm, and generating the next read-only memory address; and an arithmetic and register circuit containing an adder, a group of working registers, a group of data storage registers forming a stack for roll down operation, and a constant storage register. These circuits are interconnected by a multiple line buss system.

Patent
12 Nov 1974
TL;DR: In this paper, a train of timing pulses is obtained from one bit output of the adder; the rate of these pulses is directly related to the value of the selected timing number.
Abstract: Timing signals of adjustable rate are estabilished digitally in an electronic musical instrument through the use of digital timing numbers. A selected one of such numbers is repetitively added to the contents of an accumulating adder at a fixed rate. A train of timing pulses is obtained from one bit output of the adder; the rate of these pulses is directly related to the value of the selected timing number. Alternatively, consecutively updated parallel bit timing codes can be obtained from plural bit outputs of the accumulating adder. These timing codes, which are incremented or decremented in value by amounts established by the selected timing number, are useful for directly addressing a memory containing a set of musical instrument factors that are to be utilized on a time dependent basis.

Patent
03 Oct 1974
TL;DR: In this paper, each item in a transaction has a card or ticket having markings signifying its price and category in machine readable form, and the ticket is inserted into an automatic read-out system.
Abstract: Each item in a transaction has a card or ticket having markings signifying its price and category in machine readable form. As each item is purchased, the ticket is inserted into an automatic read-out system. The price and category markings are transduced into signals stored in a first and second buffer storage, respectively. A code converter connected to the second buffer storage operates to furnish a pulse to a corresponding one of a plurality of counters in response to each category signal. The signals in the first buffer storage are added, in turn, by a price adder whose final output therefor shows the total price of all items in the transaction. A grand total adder operates in parallel with the price adder and is cleared after predetermined time periods rather than after each transaction. The signals from the price adder and the grand total adder are supplied through multiplexers to series display and printout devices. A switch is furnished to convert the system to a computer only by disabling the print-out, display, and grand total circuits.

Patent
Don W Aldridge1
02 Jan 1974
TL;DR: In this article, a control circuit for determining the upper, lower and number of discrete, consecutive frequencies provided by a phase-locked loop is described, which includes a BCD adder having output terminals connected to the divide-by-N counter of a phase locked loop.
Abstract: Various embodiments of a control circuit which are suitable for determining the upper, lower and number of discrete, consecutive frequencies provided by a phase locked loop are disclosed. The control circuit includes a BCD adder having output terminals connected to the divide-by-N counter of a phase locked loop. BCD switches are connected to a first set of input terminals of the adder and are settable to determine the lower frequency limit of the output signal of the synthesizer. A decade counter, which is driven by a scan clock circuit, is connected to other input terminals of the BCD adder and selectively increments the divisor of the divide-by-N counter. Programmable logic circuitry is utilized to monitor the output signal of the decade counter for controlling the total number of discrete frequencies provided. Other programmable logic circuitry is utilized to monitor the output of the BCD adder to control the upper frequency limit for the output signal of the synthesizer scan. Additional BCD adders and switches are included to increase the total number of discrete frequencies provided.

Patent
26 Nov 1974
TL;DR: In this article, the adder and adder input circuits allow direct comparison of the contents of an addressed RAM word and the contents in the accumulator, or a constant and the address register.
Abstract: A greatly simplified calculator circuit implemented, for example, utilizing I 2 L technology, is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator which permits direct instruction compares while reducing the number of ROM instructions required and hence the size of the ROM to permit fabrication on the smaller chip is embodied in the present invention. The adder and adder input circuits allow a direct comparison of the contents of an addressed RAM word and the contents of the accumulator, a constant and the contents of the accumulator, or a constant and the contents of the RAM address register.

Patent
13 May 1974
TL;DR: In this article, a time multiplexed digital filter including a coefficient generator, a delay device, a multiplier, and an adder, having an AND-gate switch in the adder/delay device loop for controlling the recursive input to the adders.
Abstract: A time multiplexed digital filter including a coefficient generator, a delay device, a multiplier, and an adder, having an AND-gate switch in the adder/delay device loop for controlling the recursive input to the adder.

Patent
Eric A. Slutz1
26 Jul 1974
TL;DR: The circulating shift register time-keeping circuit of the present invention comprises five circulating shift registers and controller and time base circuits to provide real-time, stopwatch, date and alarm functions to an eight-digit display means via a display register.
Abstract: The circulating shift register time-keeping circuit of the present invention comprises five circulating shift registers and controller and time base circuits to provide real-time, stopwatch, date and alarm functions to an eight-digit display means via a display register. The real-time, stopwatch and date registers each include a binary adder, adder controller and auxiliary register coupled to clocked delay elements. The alarm register includes a comparator coupled to similarly clocked delay elements. Timing and command signals are provided to the five shift registers from the time base and controller, respectively.

Patent
26 Nov 1974
TL;DR: In this article, a simplified I2L calculator circuit is implemented on a relatively small semiconductor chip, and a unique feature of such calculator is a universal condition latch which is so connected as to permit the state thereof to be determined by multiple sources while reducing the number of ROM instructions required.
Abstract: A greatly simplified calculator circuit implemented, for example, utilizing I2 L technology, is fabricated on a relatively small semiconductor chip resulting in high yield. A unique feature of such calculator is a universal condition latch which is so connected as to permit the state thereof to be determined by multiple sources while reducing the number of ROM instructions required and hence the size of the ROM to permit fabrication on the smaller chip. The condition latch state is determined, for example, by the logical OR of up to four flags after a test flag instruction, by the logical OR of up to four keyboard inputs after a test key instruction, by the carry output of the adder after any add instruction, or by the results of an adder compare after any compare instruction.

Patent
16 Apr 1974
TL;DR: Demodulator assembly for m data trains, with differential phase modulation, comprising, for each train, an elementary demodulator dimensioned over one bit, whereas the coding is effected over a space of n intermediate bits.
Abstract: Demodulator assembly for m data trains, with differential phase modulation, comprising, for each train, an elementary demodulator dimensioned over a space of one bit, whereas the coding is effected over a space of n intermediate bits, comprising, for each train, a shift register having n+1 flip-flops in a functional connection with an adder.

Journal ArticleDOI
TL;DR: The design of fault-tolerant carry- save adders is presented and how carry-save adders can be well used as a logic unit and thus some broader application of the design is illustrated.
Abstract: In this correspondence a design of fault-tolerant carry-save adders is presented. The design of fault-tolerant carry-save adders is of practical interest since in most of the modem day computers a carry-save adder is an essential circuit. We will also indicate how carry-save adders can be well used as a logic unit and thus some broader application of the design is illustrated.