Showing papers on "Adder published in 1983"

Geometric-arithmetic parallel processor

Abstract: A plurality of identical processor cells arranged interconnected to form a data processor for processing digital data signals. Each of the cells includes an arithmetic processing element having three input terminals and two arithmetic output terminals. A plurality of memories connected to said arithmetic processing element are individually controllable to supply selected ones of a plurality of predetermined data signals to the input terminals of said processing element in response to control signals from a controller. The memories are connected to the arithmetic processing element and the controller such that both logical and arithmetic operations are performed by the arithmetic element. The data processor includes n times m cells interconnected in an m by n matrix with interior cells and edge cells. The arithmetic processing element, preferably is a full adder having two data input terminals, a carry input terminal, a sum output terminal and a carry output terminal, and the plurality of memories includes first, second and third single-bit data registers, each selectively controllable to load one of the plurality of predetermined data signals, and a multi-bit memory such as a RAM having an output terminal and selectively addressable storage locations.

(k)-Instructions-at-a-time pipelined processor for parallel execution of inherently sequential instructions

Abstract: Equipping a secondary data flow facility with additional capability, to emulate for certain operations the simultaneous processing of the prerequisite instruction and the dependent instruction, significantly improves simultaneous pipeline processing of inherently sequential instructions (k)-at-a-time, by eliminating delays for calculating prerequisite operands. For example, Instruction A+B=Z1 followed by Instruction Z1+C=Z2 is inherently sequential, with A+B=Z1 the prerequisite instruction and Z1+C=Z2 the dependent instruction. The specially equipped secondary data flow facility does not wait for Z1, the apparent input operand from the prerequisite instruction; it simulates Z1 instead, performing A+B+C=Z2 in parallel with A+B=Z1. All data flow facilities need not be fully equipped for all instructions; the secondary data flow facility may be generally less massive than a primary data flow facility, but is more sophisticated in a critical organ, such as the adder. The three-input adder of the secondary data flow facility emulates the result of a two-input adder of a primary data flow facility, occuring simultaneously in the two-input primary data flow facility adder, adding the third operand to the emulated result, without delay. The instruction unit decodes the instruction sequence normally to control (k)-at-a-time execution where there are no instruction interlocks or dependencies; to delay execution of dependent instructions until operands become available; and to reinstate (k)-at-a-time execution in a limited number of cases by using the additional capability of the secondary data flow facility to emulate the prerequisite operands. A control unit performs housekeeping to execute the instructions.

Multiplier/adder circuit

Abstract: In one embodiment of this invention, a uniquely designed switched capacitor multiplier/adder (129) is provided which also functions as a digital-to-analog converter in a single subcircuit. The multiplier/adder, in a single operation, multiplies an analog voltage by a binary coefficient, and sums this product with a second analog voltage. The use of this unique subcircuit significantly reduces the space requirements for the construction of, for example, a speech synthesis circuit utilizing linear predictive coding over prior art circuits. This invention provides a novel structure and method which minimizes error components in the synthesized speech signal due to voltage errors inherent in the use of analog sample and hold circuits which are used to store the forward and backward prediction errors utilized in the linear predictive coding technique. Using the method of this invention, the inherent error components are alternatively inverted and not inverted upon each clock cycle of the multiplier/adder. Thus imposing a frequency of one-half the clock rate upon the error components. These error components are then removed using a notch filter which removes signals having a frequency of one-half the clock rate.

An improved residue number system digital-to-analog converter

Abstract: A new technique for Residue Number System (RNS) Digital-to-Binary or Digital-to-Analog conversion based on the Chinese Remainder Theorem allows conversion with only one level of ROM and one level of Adders. The ROM's are small (e.g., 256 x 8) and the Adders use standard binary adders. Compared to previous Chinese Remainder Theorem or Mixed-Radix-Conversion Techniques, the new technique offers conversion times which are independent of the number of Residue Number System moduli and conversion times are usually much faster than competative techniques. The new technique also allows for rounding or truncation to fewer bits and sign-detection by simple modifications to the procedure. These modifications yield particularly simple and fast hardware.

Two-pass multiplier/accumulator circuit

Abstract: A two-pass Multiplier/Accumulator Circuit is provided which performs various arithmetic operations on operands contained within an X Register 10 (FIG. 1) and a Y Register 20 and places the result in an Accumulator Register 40. The arithmetic operations are carried out by passing the product of the operands successively through an array of adders in the Adder unit 34. Each adder adds an appropriate multiple of the contents of the X Register to the Accumulator 40 or to the output of the previous adder. The multiples are selected according to the contents of the Y Register. The X and Y Registers are fully buffered so that additional data transfers and functions may be performed while an arithmetic operation is in progress in a "pipeline" manner. The circuit is also capable of indicating the maximum or minimum value in a sequence of numbers in response to a single computer instruction to the circuit.

Graph theoretic approaches to the code construction for the two-user multiple- access binary adder channel

Abstract: We relate coding for the two-user multiple-access binary adder channel to a problem in graph theory, known as the independent set problem. Graph-theoretic approaches to coding for both synchronized and nonsynchronized two-user adder channels are presented. Using the Tuŕan theorem on the independence number of a simple graph, we are able to improve the lower bounds on the achievable rates of uniquely and \delta -decodable codes for the synchronized adder channel derived by Kasami and Lin. We are also able to derive lower bounds on the achievable rates of uniquely decodable codes for the nonsynchronized adder channel. We show that the rates of Deaett-Wolf codes for the nonsynchronized adder channel fall below the bounds. Synchronizing sequences for the nonsynchronized adder channel are constructed.

On a Bit-Serial Input and Bit-Serial Output Multiplier

Abstract: A recent paper by Chen and Willoner [1] forwarded a bit-sequential input and output (LSBfirst) multiplier for positive numbers. This multiplier for n-bit operands requires 2n clocks and 2n number of five-input adder modules. In this correspondence, after a brief discussion on the different claims made by the authors of [1] and their limitations, we show that this multiplier can be realized with only n adder modules. The technique is extended to two's complement number system. Also, a more complete picture of the actual implementation is depicted. Finally, we bring to the attention an already existing multiplier which fits into the bit-sequential multiplier category.

Pipelined multiply-accumulate unit

Abstract: The present invention uses a plurality of basic cells to perform a multiply-accumulate operation. Each basic cell is essentially equivalent to a one bit full adder and two flip-flops. These basic cells are connected in such a way that the processing is said to be pipelined.

Superposed image display device

Abstract: There is provided a superposed image display device to display image signals from a plurality of image diagnostic apparatuses such as an X-ray CT apparatus (10), NMR CT apparatus (12), etc. This display device comprises memories (14, 16) to store the image signals from the CT apparatuses (10) and NMR CT apparatus (12), multipliers (20, 22) to multiply the image signals read out from the memories (14, 16) by K1 und K2, an adder (30) to add the output signals of the multipliers (20, 22), and a display device (36) to display the output signal of the adder (30).

Double integration, delta-sigma, analog-digital coder

Abstract: The invention relates to a double integration or dual slope delta-sigma coder. This coder comprises a first adder receiving on an input (36) a signal E(p) to be encoded and on an input (37) the coded signal S(p), a first integrator receiving on an input (32) an output signal of the first adder, a second adder receiving on an input (38) the output signal (31) of the first integrator, an input (39) of the second adder receiving a signal proportional to the coded signal, a second integrator connected to the second adder, a quantizer circuit (43), whereof one input (D) is connected to an output (41) of the second integrator, an output Q of said quantizer circuit supplying the coded signal S(p), wherein the integrators and adders are constituted by circuits comprising operational amplifiers (30, 40) and switched capacitor arrangements (35, 36, 45, 46).

Monolithic fast fourier transform circuit

Abstract: A fast Fourier transform circuit formed on a single chip, including a fast multiplier-accumulator circuit which, in the preferred embodiment, employs a modified form of Booth's algorithm, an adder circuit, a read-only memory for storing FFT twiddle factors, and a random access memory for holding a set of input complex quantities and for receiving intermediate and final results in an in-place FFT operation. In the preferred embodiment, the FFT twiddle factors are stored in Booth's code for greater speed of operation. Control and timing circuitry on the same chip generates control signals and address codes in order to perform a sequence of butterfly computations by repeated use of the multiplier-accumulator and adder circuits, to generate FFT coefficients in the random access memory.

Focus servo system having object lens protection circuit for an optical disc player

Abstract: A focus servo system for an optical video disc player. A pair of signals generated by two pairs of photo-cells are supplied to an adder and a differential amplifier, an output signal of the adder is supplied to a first comparator and an output signal of the differential amplifier is supplied to a second comparator. When an output signal of the adder reaches a reference voltage of the first comparator, a focus servo pull-in range is detected. Thereafter, when an output signal of the differential amplifier reaches a reference voltage of the second comparator, a stable operation condition of the focus servo system is detected and a servo system loop is closed so that a malfunction is prevented.

Design of two easily-testable VLSI array multipliers

Abstract: Array multipliers are well-suited to VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are very difficult to test. This paper shows that, with appropriate cell design, array multipliers can be designed to be very easily testable. An array multiplier is called c-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures are studied. The conventional design of the carry-save array multipler is shown to be not c-testable. However, a modified design, using a modified adder cell, is generated and shown to be c-testable and requires only 16 test patterns. Similar results are obtained for the baugh-wooley two's complement array multiplier. A modified design of the baugh-wooley array multiplier is shown to be c-testable and requires 55 test patterns. The implementation of a practical c-testable 16*16 array multiplier is also presented. 10 references.

Interlaced programmable logic array having shared elements

Abstract: A programmable PLA circuit in which an interlaced AND/OR array is provided which has both common input and common output lines. Separate AND and OR functions are generated during two different timing intervals such that both of the logical arrays can physically share input and output circuit elements. A binary adder is described in which pairs of array output lines are applied to the same Exclusive-NOR circuits during the two time intervals to provide the Exclusive-NOR of product terms during the AND array time interval and to provide the Exclusive-NOR of sum of product terms or the sum of the Exclusive-NOR of product terms during the second time interval.

N-bit carry select adder circuit having only one full adder per bit

Abstract: An n-bit adder circuit, where n is an integer, for providing carry select addition of two input numbers is provided. A rank ordered plurality of section adders each have a plurality of full adders. Each full adder utilizes a single half adder to provide two sum bits which are coupled to a multiplexer which is an integral part of each section adder. One sum is for a carry-in and the other sum is for no carry-in. A method of minimizing logic circuitry which provides carry bits and carry sum select bits is provided. The carry bits and carry sum select bits control which of the two sums are provided by each section adder. By providing the carry bits and carry sum select bits in complement form every other order of section adder, logic circuitry and logic gate delays are minimized.

The design of two easily-testable VLSI array multipliers

Abstract: Array multipliers are well-suited for VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are very difficult to test. This paper shows that, with appropriate cell design, array multipliers can be designed to be very easily-testable. An array multiplier is called C-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures are studied. The conventional design of the carry-save array multiplier is shown to be not C-testable. However, a modified design, using a modified adder cell, is generated and shown lo be C-testable and requires only 76 test patterns. Similar results are obtained for the Baugh-Wooley two's complement array multiplier. A modified design of the Baugh-Wooley array multiplier is shown to be C-testable and requires 55 test patterns. The implementation of a practical C-testable 16 × 16 array multiplier is also presented.

Residue Arithmetic and VLSI

Abstract: In the residue number system arithmetic is carried out on each digit individually. There is no carry chain. This locality is of particular interest in VLSI. An evaluation of different implementations of residue arithmetic is carried out, and the effects of reduced feature sizes estimated. At the current state of technology the traditional table lookup method is preferable for a range that requires a maximum modulus that is represented by up to 4 bits, while an array of adders offers the best performance fur 7 or more bits. A combination of adders and tables covers 5 and 6 bits the best. At 0.5 mu m feature size table lookup is competitive only up to 3 bits, These conclusions are based on sample designs in nMOS.

Digital parallel computing circuit for computing p=xy+z in a shortened time

Abstract: To increase the computing speed when forming the product of a first binary number (x) and a second binary number (y) and then adding (xy+z) a third binary number (z) by means of a multiplier (mw) and an adder (aw), the individual full-adder stages of the adder (aw) except the stage for the sign digit are inserted as an additional row between the next to the last row and the output row of the multiplier, the full-adder for the sign digit of the output row (az) being also omitted. The two omitted stages are replaced with a sign-correcting stage (vk).

Automatic oscillator frequency control system

Abstract: A frequency control system is provided which makes an initial correction of the frequency (f CLK ) of its own timing circuit (50, 52, 54, 56) after comparison against a frequency (f REF ) of known accuracy and then sequentially checks and corrects the frequencies of several voltage (13a 13e) controlled local oscillator circuits (12a 12e) The timing circuit initiates the machine cycles of a central processing unit (30) which, over a sampling interval having a duration of a fixed number of machine cycles, applies a frequency index (FI) to an input register (22) in a modulo-sum frequency divider stage (20) and enables a multiplexer (16) to clock an accumulator register (26) in the divider stage (20) with a cyclical signal derived from the oscillator circuit being checked Upon expiration of the interval, the processing unit (30) compares the remainder (FN) held as the contents of the accumulator (26) against a stored zero-error constant and applies an appropriate correction word (CW) to a correction stage (60a, 62a, 64a, 60e, 62e, 64e) to shift the frequency of the oscillator being checked A signal taken from the accumulator register (26) may be used to drive a phase plane ROM (94) and, with periodic shifts in the applied frequency index (FI), to provide frequency shift keying of the applied resultant output signal Interposition of the phase adder (90) between the accumulator register (26) and phase plane ROM (94) additionally permits phase shift keying of the output signal by periodic variation in the value of a phase index (PI) applied to one input port of the phase adder (90) An overflow signal may be taken from an adder (24) in the frequency divider stage (20) to drive an auxiliary counter (120) to provide a prescaling number which can be used by the central processing unit (30) to expand the correction range of the control system

Pipeline active filter utilizing a booth type multiplier

Abstract: Multiplier units of the modified Booth decoder and carry-save adder/full adder combination are used to implement a pipeline active filter wherein pixel data is processed sequentially, and each pixel need only be accessed once and multiplied by a predetermined number of weights simultaneously, one multiplier unit for each weight. Each multiplier unit uses only one row of carry-save adders, and the results are shifted to less significant multiplier positions and one row of full adders to add the carry to the sum in order to provide the correct binary number for the product Wp. The full adder is also used to add this product Wp to the sum of products ΣWp from preceding multiply units. If m×m multiplier units are pipelined, the system would be capable of processing a kernel array of m×m weighting factors.

Burst-error correcting system

Abstract: In a digital signal transmission system, a predetermined number of words of digital information signals are added bit by bit in a modulo 2 adder to produce a first parity signal. The information signals and the first parity signal are delayed so as to have different delay times to each other, and the signals thus delayed are again added bit by bit in a modulo-2 adder to produce a second parity signal. The predetermined number of words of information signals and first and second parity signals are serially transmitted through a transmission line.

Contour correcting circuit

Abstract: A contour correcting circuit emphasizes the contour of a video signal by increasing the rise and fall characteristics of the signal by using a high frequency extraction circuit in combination with a delay circuit and an adder adding in the delay output to the extracted signal. An amplitude limiter limits the adder output to between upper and lower limits of the input video signal and a second delayed signal.

Fast Fourier transform apparatus with data timing schedule decoupling

Abstract: A fast Fourier transform (FFT) apparatus with data timing schedule decoupling is provided for obtaining the Fourier spectrum, fm, of a sequence of N data: S0, S1 . . . SN-1, derived from a time variable function, St. The apparatus is operative for performing α sets of N/2 pairs of "butterfly" operations of the general form: A(x)'=A(x)+W.sub.(z) ·A(y) and A(y)'=A(x)-W.sub.(z) ·A(y), wherein A(x) and A(y) are data terms to be operated on and W.sub.(z) is a predetermined "pointer" into a corresponding matrix or phase angle library; α is determined by the relationship N=2.sup.α. Comprising the apparatus are a first, A(x), A(y) data memory, a second, W.sub.(z) data memory, a multiplier accumulator (MAC) and an adder/subtractor. First data buffering means are disposed between the first memory and the MAC and adder/subtractor to buffer the flow of A(x), A(y) data from the first memory to the MAC and adder/subtractor, and second data buffering means are disposed between the MAC and the adder/subtractor to buffer the flow of W.sub.(z).A(y) data from the former to the latter, the data flow buffering thereby decoupling the timing schedules for data transfer and for data use. In a disclosed wrap-around FFT, third data buffering means are disposed between the adder/subtractor and the first memory to buffer the flow of A(x)' and A(y)' data from the adder/subtractor to the first memory.

Controller of pwm inverter

Abstract: PURPOSE:To reduce the magnetic sound of a motor on the basis of a PWM control by varying the hysteresis width of comparing means having hysteresis characteristic for comparing a current command signal with a current detection signal by an AC signal such as a triangular wave. CONSTITUTION:An induction motor 4 is driven by a PWM inverter 3 connected to a rectifier 1. A current command signal iu*, iv* formed of a speed command 14 and a signal of a speed detector 5 and iw* added by an adder 7, and a signal added by an adder 9 with the signals of current detectors 8U, 8V are applied to comparators 10U, 10V, 10W having hysteresis characteristic, an inverter 3 is controlled to be fired, and a triangular AC signal from a signal generator 12 is applied to a hysteresis width regulator 13 to regulate the hysteresis width of the comparators 10. Accordingly, the harmonic waves of the motor current are reduced, the magnetic sound of a motor can be largely reduced particularly at the low speed rotation time.

Method and apparatus for calculating the residue of a signed binary number

Abstract: Method and apparatus for calculating the residue of a signed binary number of "n" bits with respect to a given check base m where m=2 b -1. The bits of the binary number excluding the sign bit are partitioned into number segments, each of b bits starting with the least significant bit. If (n-1) is not an even multiple of b, higher order bit positions of the number segment containing the next most significant bit of the binary number are filled with logical zeros. A sign segment of b bits is formed. Both number and sign segments have boundaries. The bit position in the sign segment relative to a sign segment boundary which corresponds to the bit position of the sign bit "s" relative to the nearest boundary of a number segment is filled with a logical zero. All other bit positions of the sign segment are filled with the sign bit. The number and sign segments are applied to carry save adders to reduce the number segments and sign segment to a single sum segment and a single rotated carry segment. A rotated carry segment is a carry segment produced by a carry save adder, the most significant bit of which becomes the least significant bit of the rotated carry segment. The other bits of the carry segment and their significance are increased by one in the rotated carry segment. Carry segments produced by carry save adders of one level are converted to rotated carry segments before being applied to a carry save or full adder of a lower level. The single sum segment and single rotated carry segment produced by the lowest level carry save adder is applied to a one's complement adder. The b bit output of the one's complement adder is the residue of the signed binary number to the check base (2 b -1).

Voltage adder circuit

Abstract: A voltage adder circuit for adding both balanced and unbalanced input signals. The balanced input signal is applied to respective transistors of a differential transistor pair, while the unbalanced input is applied to the emitter of an input transistor having a base-collector connected across the load of one side of the differential transistor pair. The output is taken from the load on the other side of the differential transistor pair, at the emitter of an output transistor having a base-collector coupled across the second load. The voltage adder at a circuit of the present invention may further be used in a low-distortion transistor circuit.

Auto flesh circuitry as for a digital TV receiver

Abstract: A digital TV receiver includes circuitry for performing hue control by rotation of the axes of the I and Q color mixture signals. The I and Q color mixture signals are time division multiplexed and applied to a multiplicand input port of a multiplier circuit. The sines and cosines of the angle by which the I and Q vectors are to be rotated are also applied to the multiplier wherein alternate pairs of the I and Q signals are multiplied by the sine terms and intervening pairs of the I and Q signals are multiplied by cosine terms. The signal from the multiplier is applied to a delay element which delays successive samples by one sample period. Delayed and nondelayed signal samples are applied to an ADDER which produces the algebraic sums Icos φ+Qsin φ and Qcos φ-Isin φ corresponding to the desired modified I and Q signals respectively. The sums from the ADDER are demultiplexed by latches to generate separate I and Q signals.

Digital adder including counter coupled to individual bits of the input

Abstract: An adder circuit is described for producing signals representative of the sum of large numbers of block-synchronized digital signals each of which may have any value within the range of quantizing levels represented. The adder circuit includes one or more binary counters coupled to count bits of the input signal having a particular significance. Counting takes place during an active interval such as a television field interval, and the counters are reset after each counting interval. The counter outputs are latched either before or after processing by addition of other counter outputs. The latched signal represents the sum of the values of the words in one sync block.

Address arithmetic circuit of a memory unit utilized in a processing system of digitalized analogue signals

Abstract: A signal address arithmetic circuit is used for performing address arithmetic required for executing such analog signal algorithms as adaptive predicative coding, adaptive bit allocation in predictive coding, adaptive transform coding, etc The address arithmetic circuit is constructed of two counters, three registers, two selectors, a shift circuit an adder and AND gate circuits The first selector selects either one of the first counter, the second counter or a first register, and its output is applied to one input terminal of the adder The second selector selects either one of the second counter or the third register and its output is directly applied to the other input of the adder The output of the adder and the content of the second register for each bit are applied to the AND gate circuits and its output is set in the third register, the content thereof being used for memory addressing According to the type of processing algorithms and corresponding addressing modes, the arithmetic circuit performs the resetting or incrementing of the two counters, controlling the selection operation of the two selection circuits, controlling the number of shifts of the shift circuit, and resetting the third register

Full adder using transmission gates

Abstract: A binary full adder, including provision for carry digits, is implemented using metal-oxide semiconductor field-effect transistors (MOSFET) in the exclusive-OR configuration. The improved structure realizes economies in space occupancy, and device topology, reduction in power requirement and no loss in propagation time over prior full adders employing conventional logic structures.