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Showing papers on "Adder published in 1984"


Journal ArticleDOI
TL;DR: The testability of two well-known array multiplier structures is studied in detail and it is shown that, with appropriate cell design, array multipliers can be designed to be very easily testable.
Abstract: Array multipliers are well suited for VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are difficult to test. This correspondence shows that, with appropriate cell design, array multipliers can be designed to be very easily testable. An array multiplier is called C-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures is studied in detail. The conventional design of the carry–save array multiplier is modified. The modified design is shown to be C-testable and requires only 16 test patterns. Similar results are obtained for the Baugh–Wooley two's complement array multiplier. A modified design of the Baugh–Wooley array multiplier is shown to be C-testable and requires 55 test patterns. The C-testability of two other array multipliers, namely the carry–propagate and the TRW designs, is also presented.

117 citations


Patent
Edward J. Nossen1
28 Dec 1984
TL;DR: In this paper, a phase modulator includes a digital frequency word generator, an adder and a register arranged to generate recurrent digital sawtooth signals at a carrier rate, which are then converted to analog signals.
Abstract: A phase modulator includes a digital frequency word generator, an adder and a register arranged to generate recurrent digital sawtooth signals at a carrier rate. A second digital adder is coupled to receive the sawtooth signals and also receives digital information signals. The adder produces recurrent digital sawtooth signals phase-modulated by the information signal. A pair of adders receive the digital sawtooth signals and mutually sign-reversed digital information signals to produce a pair of oppositely phase-modulated constant-amplitude signals in a pair of channels. A sine memory is addressed by the phase-modulated digital sawtooth signals to produce phase-modulated sinusoidal-representative digital signals. The digital signals are then converted to analog signals. Since the two channels contain signals which are phase-modulated but not amplitude-modulated, the signals may be amplified by nonlinear amplifiers. An adder is coupled to the outputs of the two channels to sum together the two phase-modulated signals to produce an amplitude-modulated signal. Combinations of amplitude and phase modulation may be generated by a combined structure.

80 citations


Patent
Tim A. Williams1
14 Dec 1984
TL;DR: In this paper, an adder/subtractor circuit which efficiently effects addition and subtraction of operands in logarithmic number representation over a wide dynamic range is provided.
Abstract: In a digital signal processing system, a logarithmic arithmetic logic unit is provided which selectively performs multiply/accumulate operations of operands in logarithmic number representation. Direct feed through of operands through an adder/subtractor circuit, even when an addition or subtraction is not effected, eliminates external bypass circuitry. A method for adding and subtracting operands in logarithmic number representation is provided. An adder/subtractor circuit which efficiently effects addition and subtraction of operands in logarithmic number representation over a wide dynamic range is provided.

69 citations


Journal ArticleDOI
TL;DR: A new type of convolver is presented which utilizes a kind of systolic array where the basic cell is mainly a full adder and the basic structure is a serial/parallel multiplier.
Abstract: A new type of convolver is presented. This type utilizes a kind of systolic array where the basic cell is mainly a full adder and the basic structure is a serial/parallel multiplier. A new formalism is developed which encompasses the whole family of serial/parallel multipliers. All these designs can be carried over to the design of convolvers since the convolution formula has the same structure on the word level as the multiplier on the bit level. Furthermore, the whole convolver can be embedded in one single uniform bit-serial one-dimensional structure. This extremely pin-saving and VLSI-oriented design can also be used for recursive filters and for 2D signal processing. Programmability (using a structure with varying precision and kernel size) can be traded for simplicity and efficacy. The paper contains comparative discussions of other convolvers; however, actual hardware performance is not given.

62 citations


Patent
10 Sep 1984
TL;DR: A decimation-in-frequency fast-Fourier-transform butterfly circuit for performing a radix-four butterfly operation includes a first group of adders (86, 88, 90, and 92), a second group of removeers (70, 72, 74, and 76), and a group of twiddle factor multipliers (78, 80, and 82) that are interconnected in such a way as to perform the radix four fast-fourier transform algorithm.
Abstract: A decimation-in-frequency fast-Fourier-transform butterfly circuit for performing a radix-four butterfly operation includes a first group of adders (86, 88, 90, and 92), a second group of adders (70, 72, 74, and 76), and a group of twiddle-factor multipliers (78, 80, and 82) that are interconnected in such a way as to perform the radix-four fast-Fourier-transform algorithm. Additionally, bypass lines (102, 104, 106, and 108) bypass the first group of adders, and switches (94, 96, 98, and 100) switch between the signals on the bypass lines and those from the first group of adders. As a result, the circuit performs a radix-four FFT operation when the switches are in one state, and it performs two radix-two FFT butterfly operations simultaneously when the switches are in the other state.

61 citations


Patent
13 Nov 1984
TL;DR: In this paper, a pipelining-based vector dot multiplier is proposed for positive integer dot multiplication, where a latch interconnects the carryout of each adder in a row to the carry-in of another adders in the same row, and the sum output is accumulated in an adder according to the length of the vectors to be processed.
Abstract: Vector dot multiplication is facilitated in a multiplier in which pipelining techniques are employed. Two vectors u(i), v(i), each having the same number of components (L), the components of the vector u(i) having m bits, and the components of the other vector v(i) having n bits per component. For example, a classical positive integer dot multiplier includes m-1 multiplier rows with each multiplier row having n+1 multiplying stages, each stage including an adder and latches. A latch interconnects the carry-out of each adder in a row to the carry-in of another adder in the same row, and a latch interconnects the sum output of each adder in a row to an input of another adder in another row. The result is accumulated in an adder according to the length of the vectors to be processed. 2's compliment number multiplication is accommodated by stretching each multiplier row by connecting two full adders serially therewith. Additionally, an inverter inverts the words u(i) and then applies the inverted words to the last multiplier row along with the sign bit for the other vector v(i). The same concept may be used to implement a variety of multipliers and floating point dot multipliers.

58 citations


Patent
Tim A. Williams1
14 Dec 1984
TL;DR: In a digital signal processing system, a logarithmic arithmetic logic unit which selectively performs multiply/accumulate operations of operands in log-carithmic number representation is used to eliminate external bypass circuitry.
Abstract: In a digital signal processing system, a logarithmic arithmetic logic unit which selectively performs multiply/accumulate operations of operands in logarithmic number representation. Direct feed through of operands through an adder/subtractor circuit, even when an addition or subtraction is not effected, eliminates external bypass circuitry. A method for adding and subtracting operands in logarithmic number representation. An adder/subtractor circuit which efficiently effects addition and subtraction of operands in logarithmic number representation over a wide dynamic range.

58 citations


Journal ArticleDOI
01 Oct 1984
TL;DR: A 32-bit CMOS floating-point multiplier is described, designed for compatibility with 16-bit microcomputer systems, and fabricated in 2-/spl mu/m n-well CMOS technology.
Abstract: A 32-bit CMOS floating-point multiplier is described. The chip can perform 32-bit floating-point multiplication (based on the proposed IEEE Standard format) and 24-bit fixed-point multiplication (two's complement format) in less than 78.7 and 71.1 ns, respectively; the typical power dissipation is 195 mW at 10,000,000 operations per second. High-speed multiplication techniques, a modified Booth's algorithm, a carry save adder scheme, a high-speed CMOS full adder, and a modified carry select adder are used to achieve the above high performance. The chip is designed for compatibility with 16-bit microcomputer systems, and is fabricated in 2-/spl mu/m n-well CMOS technology; it contains about 23000 transistors 5.75/spl times/5.67 mm/SUP 2/ in size.

54 citations


Patent
Ootani Susumu1
10 Oct 1984
TL;DR: In this paper, an add-compare-select circuit is provided for each state in a given time slot of a Viterbi trellis diagram, which includes first and second pairs of adders coupled to a source of sequentially updated path metrics and to a branch metric generator which generates sums of branch metrics over successive time slots.
Abstract: In an error correcting apparatus, an add-compare-select circuit is provided for each state in a given time slot of a Viterbi trellis diagram. The ACS circuit includes first and second pairs of adders coupled to a source of sequentially updated path metrics and to a branch metric generator which generates sums of branch metrics over successive time slots. The updated path metrics of states two time slots prior to the given time slot and the branch metric sums are added up in the adders. The outputs of adders in pairs are compared respectively by first comparators to determine the highest of the adder outputs. The determined highest values are passed through first selectors to a second comparator to further determine the highest of the selected adder outputs, the further determined value being passed through a second selector to the path metric source to update the previous value. Control signals indicating the determinations taken by the first and second comparators are coupled to a path memory for storing data indicating the paths of the selected values.

50 citations


Patent
10 Dec 1984
TL;DR: A halftone image recording apparatus has a photoelectric converter for generating a density signal representing the density level of an image, a periodical or random signal generator for periodically or randomly generating level signals, an adder for adding the density signal and the level signal, a memory for storing the addition signal from the adder, a pattern generator for generating image pattern, and an ink jet head or the like to record the image pattern as mentioned in this paper.
Abstract: A halftone image recording apparatus has a photoelectric converter for generating a density signal representing the density level of an image, a periodical or random signal generator for periodically or randomly generating level signals, an adder for adding the density signal and the level signals, a memory for storing the addition signal from the adder, a pattern generator for generating an image pattern, and an ink jet head or the like to record the image pattern. Pseudooutlines are eliminated without requiring an increase in the reading resolution and without imparing the resolution during recording. Input image data is compressed and a memory of smaller capacity can be used.

47 citations


Patent
20 Mar 1984
TL;DR: In this article, the authors proposed a solid-state imaging apparatus where photo signals are read out through MOS type FETs from photosensors such as photodiodes, arrayed in two dimensions in large numbers.
Abstract: This invention relates to a solid-state imaging apparatus wherein photo signals are read out through MOS type FETs from photosensors, such as photodiodes, arrayed in two dimensions in large numbers. The invention improves the signal-to-noise ratio of the output signal by reducing or eliminating noise components mixed in the photo signal. Analysis of the noise components has revealed a correlation in which a noise component of a certain polarity develops again with the opposite polarity after a period that is shorter than one horizontal scanning period by the duration of one horizontal scanning pulse. To take advantage of this correlation, the apparatus provides a processing circuit that includes a delay circuit and an adder circuit to act together to cancel the noise.

Patent
22 Aug 1984
TL;DR: In this article, a method and apparatus for predicting the condition code of a condition-code-setting instruction by comparing operands in a data processing system is presented, where an operand comparator includes one or more half-adders to predict carry outs at an early time.
Abstract: Disclosed is a method and apparatus for predicting the condition code of a condition-code-setting instruction by comparing operands in a data processing system. An operand comparator includes one or more half-adders to predict carry outs at an early time. The comparator is used in a data processing system which is operative in response to instructions having operation codes for specifying operations to be executed. The instructions also have operand fields for identifying operands to be utilized in connection with executing the instructions.

Journal ArticleDOI
TL;DR: Coding schemes for the noiseless T -user binary adder multiple-access channel are discussed and a class of uniquely decodable codes of arbitrary length satisfying a specific recursive relationship is explicitly constructed.
Abstract: Coding schemes for the noiseless T -user binary adder multiple-access channel are discussed. A class of uniquely decodable codes of arbitrary length satisfying a specific recursive relationship and which are asymptotically good is explicitly constructed.

Patent
Masahiko Achiha1
23 Jul 1984
TL;DR: A motion detecting circuit suitable for detecting object-movement on an interlaced TV signal includes at least three field memories, subtracters, absolute circuits and an adder circuit as mentioned in this paper.
Abstract: A motion detecting circuit suitable for detecting object-movement on an interlaced TV signal includes at least three field memories, subtracters, absolute circuits and an adder circuit. The motion detector evaluates object-movement by accumulating frame difference signals between adjacent fields.

Patent
Toru Ohtsuki1, Ooshima Yoshio1, Sako Ishikawa1, Hideaki Yabe1, Masaharu Fukuta1 
27 Jun 1984
TL;DR: In this article, an apparatus for decimal multiplication divides a multiplier of binary coded decimal into plural groups, generates plural partial products of which are multiplied a multiplicand of BCD and the plural groups of multiplier over successive cycles and adds them to an intermediate product which is a summation of the previously generated partial products.
Abstract: An apparatus for decimal multiplication divides a multiplier of binary coded decimal (BCD) into plural groups, generates plural partial products of which are multiplied a multiplicand of BCD and the plural groups of multiplier over successive cycles and adds them to an intermediate product which is a summation of the previously generated partial products. The addition of the partial product and the intermediate product is made by a carry save adder. At a first cycle, the intermediate product is set to zero, and the addition of 6 is made to each digit of either one of the intermediate product sum and the partial product, and the addition of the partial product and the intermediate product is made by a carry save adder loop over successive cycles. At a final cycle, the sum and carry from the carry save adder are added by a full adder, and the subtraction of 6 is made for each digit according to the existence of carry transfer in each digit of the full adder and the resultant value is output as a multiplication result.

Patent
24 Jan 1984
TL;DR: In this article, a fixed-point data/floating point data converting apparatus has been proposed, in which a priority encoder with input terminals respectively receiving output signals from logic gates (first logic gates) for use in detecting whether or not all of the digits fixed point data are "0", to obtain a number of continuous "zero" digits from the most significant digit.
Abstract: A fixed-point data/floating-point data converting apparatus has: a priority encoder with input terminals respectively receiving output signals from logic gates (first logic gates) for use in detecting whether or not all of the digits fixed-point data are "0", to obtain a number of continuous "zero" digits from the most significant digit of the fixed-point data, in accordance with the contents of the signals received thereby; a shifter for shifting the fixed-point data to the left by the number of digits of continuous "zero" digits, thereby obtaining a mantissa part; an adder for subtracting the number of continuous "zero" digits from a reference value, thereby obtaining an exponent part; and a data selector for generating the floating-point data in accordance with the subtraction results from the adder, the shift results from the shifter, all-zero data, and an output signal from the logic gate (first logic gate) for detecting whether or not all digits of the fixed-point data are "0", in response to the output signals from the logic gates (second logic gates). In this converting apparatus, the data selector selects the all-zero data, as floating-point data, when all of the digits of the fixed-point data are "0". Otherwise, the data selector selects, as floating-point data, data including the subtraction results supplied from the adder and the shift results supplied from the shifter.

Patent
10 May 1984
TL;DR: In this paper, an adaptive equalizer arrangement for digital transmission system comprises at the output of the transmission channel a first in-phase path and in parallel with this first path, a second quadrature path, both paths being of the non-recursive transversal filter type having n branches and (n-1) delay circuits between the inputs of these branches, each of these n branches comprising, arranged in series, a mixer, a low-pass filter, a multiplier, and having their outputs connected to an adder which is followed by a sampling circuit and thereafter by a
Abstract: An adaptive equalizer arrangement for digital transmission system comprises at the output of the transmission channel a first in-phase path and in parallel with this first path, a second quadrature path, both paths being of the non-recursive transversal filter type having n branches and (n-1) delay circuits between the inputs of these branches, each of these n branches comprising, arranged in series, a mixer, a low-pass filter, a multiplier, and having their outputs connected to an adder which is followed by a sampling circuit and thereafter by a comparator circuit to decide the symbols to be transmitted from the outputs of these paths. The arrangement also comprises a third control path which comprises two subtracting circuits to determine the differences between the signals before and after decision and a control circuit of a voltage-controlled oscillator, 2n phase shifters and 2n multipliers.

Patent
Masaru Uya1
23 Aug 1984
TL;DR: A parallel binary adder has several blocked adders, wherein numbers of bits of adders are selected to be larger in higher order blocks than lower order blocks, thereby addition in all blocks will finish at the same time as mentioned in this paper.
Abstract: A parallel binary adder has several blocked adders, wherein numbers of bits of adders are selected to be larger in higher order blocks than lower order blocks, thereby addition in all blocks will finish at the same time, thereby undue waiting time between the completion of the addition in several blocks can be eliminated, and thereby a faster parallel binary adder is obtainable.

Patent
05 Jan 1984
TL;DR: In this paper, the distance between two points is measured by providing a magnetic field generating means and an arithmetic means which transduces the magnetic field produced by the generating means into a voltage, and utilizing data on the distances between both means.
Abstract: PURPOSE:To measure the distance between two points by providing a magnetic field generating means and an arithmetic means which transduces a magnetic field produced by the magnetic field generating means into a voltage, and utilizing data on the distance between both means. CONSTITUTION:The magnetic field generator 1 is composed of coils for generatin magnetic fields in three directions. Those coils L1-L3 generate the magnetic field in the (x)-axis, (y)-axis, and (z)-axis directions. The magnetic field generator 1 is connected to a driver 2, which outputs an AC signal obtained from an oscillator 5 selectively to the coils L1-L3. A sensor 6 has coils SL1-SL3 to detect the magnetic fields in the three directions. The output of the sensor 6 is added to the square-law detected signal of a signal obtained through a detector adder 7. The output of the detector adder 7 is further processed and added through an arithmetic processing circuit 8 and then passed through a computing element 8-8 for the root of the 6th power to output a voltage proportional to the distance between the magnetic field generator and sensor. Thus, the distance between two points is measured.

Patent
30 Mar 1984
TL;DR: In this article, a parallel combinational logic system has a shortened carry run for two binarily-coded numbers upon consideration of an input carry, and two alternative carries are respectively formed, group-wise, from the sums of the operands in first-combinatorial logic units, the actual result carries being selected therefrom and from a decision logic unit, depending on other group carries.
Abstract: A parallel combinational logic system has a shortened carry run for two binarily-coded numbers upon consideration of an input carry. In order to shorten the carry throughput time, two alternative carries are respectively formed, group-wise, from the sums of the operands in first combinational logic units, the actual result carries being selected therefrom and from a decision logic unit, upon consideration of other group carries. These result carries are supplied to second combinational logic units at whose inputs the operands to be combined are applied. Under the control of the result carries, the operands are combined group-wise with one another or, respectively, the final result is selected from two alternative intermediate results.

Patent
08 Feb 1984
TL;DR: A lock-in amplifier includes a phase-sensitive detector (7) having a signal input and a reference input as mentioned in this paper, and the output signal from detector is compensated for dc offset errors which are dependent on the frequency of the reference input ad on ambient temperature changes by having a correction signal added to it in an adder.
Abstract: A lock-in amplifier includes a phase-sensitive detector (7) having a signal input and a reference input. The output signal from detector (7) is compensated for dc offset errors which are dependent on the frequency of the reference input ad on ambient temperature changes by having a correction signal added to it in an adder (11). Changes in gain are compensated for by the addition of a compensation signal in an adder (13). Phase errors are compensated by providing a phase shifter (8) for the reference input. The dc correction, gain compensation and phase correction signals are obtained from a controller (10) which provides digital signals the values of which are derived from a memory (18), a temperature transducer (17) and a reference input frequency meter (16).

Patent
11 Apr 1984
TL;DR: In this article, a pipelined adder for adding or subtracting two floating point input data each expressed by a sign data, an exponent data and a mantissa expressed in a sign-magnitude format, in accordance with an external operation mode designation signal, is presented.
Abstract: A pipelined adder for adding or subtracting two floating point input data each expressed by a sign data, an exponent data and a mantissa expressed in a sign-magnitude format, in accordance with an external operation mode designation signal to produce a floating point sum or difference data in a sign-magnitude format. In a first stage of the adder, the magnitudes of the exponent data of the input data are compared by a subtractor or a comparator and the magnitudes of the mantissa data of the input data are compared by a subtractor or a comparator. An actual operation mode for the mantissa data of the input data is determined, on the basis of the compare results of the exponent data and the mantissa data and the external operation mode designation signals, so that the operation result data is always expressed in a sign-magnitude format.

Patent
18 Dec 1984
TL;DR: In this paper, a frequency synthesizer operating with fractional division and reduced phase jumping is described, in which a controlled oscillator (11) supplying a signal of the period 1/Fs; a first analog adder (15) having an output coupled to a control input of the oscillator; and a phase comparator (9) receiving the signal supplied by the divider (8) and the reference signal, and supplying to a second output of the first adder(15) an analog signal the value of which is proportional to the phase difference between these two signals
Abstract: 1. Frequency synthesizer operating with fractional division and reduced phase jumping, comprising : - a controlled oscillator (11) supplying a signal of the period 1/Fs ; - a first analog adder (15) having an output coupled to a control input of the oscillator (11) ; - a frequency divider (8) of variable order RV, supplying a signal of the frequency Fs /RV ; - means (6) for supplying a reference signal ; - a modulo M counter (7), referred to as a phase accumulator, supplying a binary word C the value, modulo M, of which increases by a value kM at each period of the reference signal, k being comprised between 0 and 1 ; - a device (10) for the digital-analog conversion and correction, coupling a first output of the phase accumulator (7) to a first input of the first adder (15) ; - a phase comparator (9) receiving the signal supplied by the divider (8) and the reference signal, and supplying to a second input of the first adder (15) an analog signal the value of which is proportional to the phase difference between these two signals and proportional to the period 1/Fs ; characterized in that the device (10) for the digital-analog conversion and correction comprises : - a plurality of timing devices (59 to 66), each performng a timing of a duration which is proportional to the value of a determined fraction of the binary word C and proportional to the period 1/Fs ; - a plurality of sources (70 to 78) each supplying an analog signal the value of which is constant and respectively corresponds to the rate of one of the fractions of the binary word C ; - a second analog adder (79) having an output coupled to the first input of the first analog adder (15) ; - a plurality of analog switches (67 to 70) respectively connecting the sources (70 to 78) to the inputs of the second adder (79) and being respectively controlled by the timing devices (59 to 66).

Patent
17 Dec 1984
TL;DR: In this article, a circuit module rapidly calculates a discrete numerical convolution, such as finding the sum of the products of a 16 bit constant and a 16-bit variable, performed by the module which is programmable so that the constant may be changed for a new problem.
Abstract: A circuit module rapidly calculates a discrete numerical convolution. A convolution such as finding the sum of the products of a 16 bit constant and a 16 bit variable is performed by the module which is programmable so that the constant may be changed for a new problem. In addition, the module may be programmed to find the sum of the products of 4 and 8 bit constants and variables. Random access memories are loaded with partial products of the selected constant and all possible variables. Then, when the actual variable is loaded, it acts as an address to find the correct parital product in the particular RAM. The partial products from all of the RAMs are shifted to the appropriate numerical power position (if necessary) and then added in adder elements.

Patent
Otakar A. Horna1
21 May 1984
TL;DR: In this article, an echo cancellation with extended frequency range for acoustic echoes is proposed, which consists of an adaptive finite impulse response filter receiving the receive signal below a cross-over frequency and predicting the echo of this signal across the echo path, a subtractor for subtracting the predicted echo form the send signal below the crossover frequency.
Abstract: An echo canceller with extended frequency range for acoustic echoes comprising an adaptive finite impulse response filter receiving the receive signal below a cross-over frequency and predicting the echo of this signal across the echo path, a subtractor for subtracting the predicted echo form the send signal below the cross-over frequency, and an adder for combining the low frequency output of the adder with the send signal above the cross-over frequency to form the send signal to be transmitted.

Patent
07 Aug 1984
TL;DR: In this paper, an optical information recording and reproducing apparatus having a laser light source and an optical system so that a beam from the light source is irradiated through the optical system on an information recording medium to record and reproduce information is presented.
Abstract: In an optical information recording and reproducing apparatus having a laser light source and an optical system so that a beam from the laser light source is irradiated through the optical system on an information recording medium to record and reproduce information, an accousto-optic modulator is disposed in the optical system for receiving the beam from the laser light source, and a modulation unit is provided which comprises an oscillator for generating a plurality of signals at different frequencies, a modulator for modulating the outputs of the oscillator and an adder for adding together the outputs of the modulator

Patent
15 May 1984
TL;DR: In this paper, a latch register, a shift register, half adder, and full series and parallel adder circuits are described for binary trinary signals with three primary light frequencies.
Abstract: Logic devices for frequency encoded trinary logic signals are simulated by standard binary circuits. The binary circuits include frequency sensing and frequency selecting devices at the inputs and outputs thereof for decoding the frequency encoded trinary logic signals to binary level logic signals and for frequency encoding the resulting binary output to trinary logic signals. Optical encoding using the three primary light frequencies provides a convenient trinary signal format for the frequency encoded signals. A latch register, a shift register, a half adder and full series and parallel adder circuits are disclosed.

Patent
Degroot Richard Douglas1
25 Oct 1984
TL;DR: In this paper, a data processing system includes a multiple floating point arithmetic unit with a putaway and a bypass bus, which includes a new instruction for handling multiple multiply or divide instructions, including passing the results of each multiply/divide operation on a bypassbus to the input of an adder along with the inputs from an accumulate bypass bus which is the output from the adder for an automatic add operation on an accumulate multiply or accumulate divide operation.
Abstract: A data processing system includes a multiple floating point arithmetic unit with a putaway and a bypass bus, which includes a new instruction for handling multiple multiply or divide instructions. These instructions are separated by add operations, including passing the results of each multiply/divide operation on a bypass bus to the input of an adder along with the inputs from an accumulate bypass bus which is the output from the adder for an automatic add operation on an accumulate multiply or accumulate divide operation. This allows two floating point results to be produced each cycle, one of which can be accumulated without any intervening control by the central decoder. The accumulation is performed under distributed control of the accumulator logic itself.

Patent
Douglas N. Curry1
03 Aug 1984
TL;DR: In this article, a method for generating a variable frequency clock pulse for a raster scanner is described. But this method requires the use of an accumulating adder and a register loop to form an accumulator circuit, and the correction number is then supplied to the other accumulator adder input.
Abstract: A method for generating a variable frequency clock pulse for a raster scanner. First, a correction number, which may be the sum of corrections for scan-nonlinearity, polygon signature errors and motor hunt errors, is generated. This number is then added periodically to a running sum. The most significant bit of this sum is then available as the clock pulse output. The frequency of the output clock will be proportional to the correction number. The described circuit uses an accumulating adder and a register loop to form an accumulator circuit. The correction number is then supplied to the other accumulator adder input, and the register is clocked with a fixed frequency sample clock pulse.

Patent
06 Nov 1984
TL;DR: In this paper, a construction in which subtraction processing and digit shift processing in decimal division are carried out in parallel with each other to shorten the time required for decimal division was proposed.
Abstract: This invention employs a construction in which subtraction processing and digit shift processing in decimal division are carried out in parallel with each other to shorten the time required for decimal division. A dividend is stored in a register B and a divisor, in a register C. A selector 6 selects register B when the result of subtraction by an adder/subtracter 1 is positive or zero, and selects register A at other times. Both adder/subtracter 1 and a shifter 2 receive the signal from the selector 6 in the same way, and execute the subtraction processing and the shift processing, respectively. The results of these processings are stored in the registers B and A', respectively. The division time can be shortened because the adder/subtracter 1 and the shifter 2 can be actuated simultaneously.