Showing papers on "Adder published in 1986"

Automatic dynamic equalizing

Abstract: An automatic dynamic equalizer includes left and right input terminals, an input adder and left and right output adders. The left and right input terminals are connected to inputs of the input adder and inputs of the left and right output adder, respectively. The output of the input adder is connected to the input of a 2:1 compressor. The output of the 2:1 compressor is connected to the input of a bandpass filter having a transmission in the low bass frequency region centered at a frequency of about 60 Hz. The output of the bandpass filter is coupled to inputs of the left and right output adders.

Logical minimization of multilevel coded functions.

Abstract: Discrete numerical values in digital processing systems may be encoded in two-level (binary) or higher-level (multilevel) representations. Multilevel coding can produce smaller and more efficient processors. In truth-table lookup processing, the number of entries (reference patterns) can be reduced using multilevel coding. Since parallel-input/parallel-output optical truth-table lookup processors can be constructed based on holographic content-addressable memories, it is essential to know the minimum storage required to implement various functions. A new simple method for reducing multivalued functions is presented. This method is based on an extension of the Quine-McCluskey minimization method used for binary logic functions. This minimization method is then applied to the truth tables representing (1) modified signed-digit addition, (2) residue addition, and (3) residue multiplication. A programmable logic array gate configuration for the modified signed-digit adder is presented.

Digital filter switch for data receiver

Abstract: A digital filter switch for use with a data receiver incorporates first and second squaring units connected to the outputs of first and second band-pass filters tuned to the separation and character frequencies in a signal transmission. The outputs of the squaring units are interconnected via an adder to the input of a low-pass filter, which produces the output data signal.

Accumulator Compression Testing

Abstract: A new test data reduction technique called accumulator compression testng (ACT) is proposed ACT is an extension of syndrome testing It is shown that the enumeration of errors missed by ACT for a unit under test is equivalent to the number of restricted partitions of a number Asymptotic results are obtained for independent and dependent error modes Comparison is made between signature analysis (SA) and ACT Theoretical results indicate that with ACT a better control over fault coverage can be obtained than with SA Experimental results are supportive of this indication Built-in self test for processor environments may be feasible with ACT However, for general VLSI circuits the complexity of ACT may be a problem as an adder is necessary

Balanced delay trees and combinatorial division in VLSI

Abstract: Three floating-point arithmetic chips have been implemented in 1.5-/spl mu/m NMOS technology utilizing several novel circuit designs. The theories behind two of these are presented. A method is presented for constructing balanced delay trees that have a better area-time product than binary trees; one important application of these trees is in the construction of fast multipliers. Also presented is a technique for doing redundant digital division that lends itself to implementation in combinatorial VLSI.

A VLSI chip for the winograd/Prime factor algorithm to compute the discrete Fourier transform

Abstract: There is an extensive literature about computing the discrete Fourier transform and the hardware implementations of the different algorithms. In this paper, we propose a radically different approach based on the so-called small n algorithms and several different iteration methods. Our approach will result in fully pipelined bit serial architectures which require no control units. The area is about the minimum possible, and the overall delay is within an optimal order magnitude. An essential ingredient of these implementations is the use of digit on-line adder and multiplier cells.

System and method for diversity reception of signals

Abstract: A diversity reception of signals involves first and second mobile receivers which recover first and second baseband signals. The first and second receivers have first and second wave detectors, respectively, for generating output voltages corresponding to the strength of an FM modulated signal. When the difference in output voltages between the first and second detectors exceeds a predetermined value, a comparator gives an output detection signal. An adder circuit combines the first and second recovered baseband signals. First and second switching circuits selectively cut off the lower level one of the first or second recovered signal, which is then being supplied to the adder circuit. A third switching circuit adjusts the gain of the adder circuit. When the comparator does not give an output detection signal, the first and second switching circuits feed both the first and second recovered baseband signals to the adder circuit. At the same time, the third switching circuit reduces the gain of the adder circuit by one-half.

One frequency repeater for a digital radio system

Abstract: A one frequency repeater includes a receiver (2) for receiving a reception signal through a receiving antenna (1), a variable frequency characteristic filter (5) for generating a signal for cancelling an interference signal caused by leakage of a transmission signal into a receiving antenna (1), an adder (4) for adding the interference signal and the reception signal, a demodulator (7) for demodulating an output signal from the adder, a data converter (9) for converting an output signal from the modulator, a modulator (11) for modulating a carrier according to an output from the data converter (9), and a transmitter (13) for transmitting from a transmitting antenna (15) an output signal modulated by the modulator (11). The variable frequency characteristic filter (5) receives the signal modulated by the modulator (11), is controlled in response to a control signal including the output from the data converter (9), and supplies the interference cancellation signal to the adder (4).

Fast multiplierless architecture for general purpose VLSI FIR digital filters with minimized hardware

Abstract: A digital transversal filter which employs a multiplierless algorithm for effecting convolutions of samples of a digital input word by the filter coefficients. Each of the samples of an input word is bit sliced into segments of two or more bits, and convolutions are carried out in parallel on all segments using only adders and registers. The convolution products are then summed in a pipeline adder tree to derive the convolution of the complete input word. This architecture provides high frequency capability and significantly lower transistor count and hardware complexity, enabling efficient very large scale integration (VLSI) implementation.

Basic circuitry particularly for construction of multivalued logic systems

Abstract: Disclosed are basic circuits operable in a current mode in multivalued logic circuit systems, analog circuit systems and the like Examples of the basic circuits are a successor, quantizer, adder, substracter, divider, multiplier, decoder, literal circuit, equivalence circuit, bilateral T-gate, complement literal circuit and h operator circuit These basic circuits are realized by using floating threshold switching circuits, floating window switching circuits, threshold SPDT switching circuits, and the like

Distributed arithmetic realization of second-order normal-form digital filter

Abstract: A high-speed distributed-arithmetic realization of a second-order normal-form digital filter includes a filter input, a filter output, and a memory. The memory has a first input, a second input, and a third input. The first memory input is connected to the filter input. The memory also has a first output, a second output, and a third output. The digital filter additionally includes a first adder having an input connected to the first memory output, and having its output connected to the filter output. A second adder has an input connected to the second memory output, and has its output connected to the second memory input. A third adder has an input connected to the third memory output and has its output connected to the third memory input.

Arithmetic unit with simple overflow detection system

Abstract: An arithmetic unit with a simple overflow detection system performs arithmetic operations between first and second data. The first data is exclusively divided into a fixed value portion and a variable portion whose digit position is lower than that of the fixed value portion. A ratio of a bit length of the fixed value portion to that of the variable portion in the first data varies. The second data corresponds to only the variable portion of the first data. The arithmetic unit includes an adder (40) for adding the first and second data in their entire lenghts, switch circuits (50, 60) for separating output data from the first data and the adder (40) into fixed value and variable portions, a comparator (70) for comparing the fixed value portions of the outputs from the first data and the adder (40) and outputting a coincidence or noncoincidence signal, an output register (80) for linking the fixed value portion of the first data and the variable portion of the output from the adder (40) and outputting the linked data, and an overflow detector (90) for detecting an overflow in response to the noncoincidence signal from the comparator (70).

Fast BCD/binary adder

Abstract: A fast BCD/Binary Adder in which provision is made for selectively performing either binary or BCD arithmetic operations using an approach in which, for BCD addition, an appropriate correction value is always caused to be added to one of the input operands and an appropriate correction value conditionally subtracted from the result where required to give a proper BCD result. High speed operation is achieved by merging the binary input logic with the correction logic so as to provide for addition of the correction value concurrently with the addition of the input operands in a manner which automatically takes into account any inter-bit carries that may be produced by the correction value. In addition, provision is made for concurrently producing conditional sums (one assuming the presence of an input carry and the other assuming the absence of a carry) in parallel with the performance of look-ahead carry operations. An output logical selection circuit merges the selection logic for selecting the correct conditional sum (in response to the look-ahead carry produced) with the conditional subtraction logic required for BCD operation in a manner so that the two operations are performed concurrently during BCD operations.

Apparatus and method for execution of floating point operations

Abstract: In a floating point arithmetic execution unit, an additional adder unit and a selection network are added to the apparatus typically performing the arithmetic floating point function. The additional apparatus permits certain processes forming part of arithmetic operations to be executed in parallel. For selected arithmetic operations, the final result can be one of two values typically related by an intermediate shifting operation. By performing the processes in parallel and selecting the appropriate result, the execution time can be reduced when compared to the execution of the process in a serial implementation. The fundamental arithmetic operations of addition, subtraction, multiplication and division can each have the execution time decreased using the disclosed additional apparatus.

Digital optical adder based on spatial filtering

Abstract: The optical implementation of a half adder is presented, and its extension to a full adder and a ripple carry adder is described. The adder is based on a spatial filtering method using theta modulation for encoding of the binary data. Many pairs of numbers can be added in parallel. Nonreal-time laboratory experiments are described, and experimental results are shown.

Programmed time-changing coefficient digital filter

Abstract: A time-changing coefficient digital filter having a data RAM for storing input data, a purality of N data registers at the output of the data RAM forming a delay element, a coefficient RAM storing coefficient values, coefficient registers temporarily storing respective coefficients, and a multiplier for multiplying data read out of data registers and coefficient registers respectively. Data from the multiplier and inputs is accumulated in an adder. Coefficient registers and data registers are updated by data from the data RAM and coefficient RAM. The coefficient digital filter provides a sum of products sequentially read out of the coefficient and data registers. The digital filter is applied to produce a musical instrumet having improved tonal qualities.

The noncooperative binary adder channel

Abstract: Jamming is studied as a game in the binary adder channel. The legal user controls simultaneously the encoder and the decoder by the choice of a key; the jammer controls the channel by the choice of an interference signal. For any given pair of encoder and decoder, this leads to a two-person zero-sum game. It is shown that this game can be solved in many cases of interest. In particular, an exact measure of performance is derived for the class of so-called direct sequence systems.

Optical techniques for real-time binary multiplication

Abstract: An optical system which performs the multiplication of binary numbers is described and proof-of-principle experiments are performed. The simultaneous generation of all partial products, optical regrouping of bit products, and optical carry look-ahead addition are novel features of the proposed scheme which takes advantage of the parallel operations capability of optical computers. The proposed processor uses liquid crystal light valves (LCLVs). By space-sharing the LCLVs one such system could function as an array of multipliers. Together with the optical carry look-ahead adders described, this would constitute an optical matrix–vector multiplier.

Multiplierless FIR digital filter with two to the Nth power coefficients

Abstract: A multiplierless digital FIR filter comprising a plurality of serially cascaded stages providing a non-linear series of two to the Nth power coefficient values, and in which quantization error is reduced by scaling the coefficient values to minimize root mean square error. Each stage includes a basic unit and an incremental unit, the basic unit providing two shift operations and including a delay element and an adder. To achieve a particular quantization error, one or more incremental units are connected in series with the basic unit in each stage, each such incremental unit providing a single shift operation and including a delay element and an adder. The number of incremental units in each stage and the number of cascaded stages can be selected to achieve a filter having desired performance characteristics and which can be realized on a VLSI chip.

Digital Optical Logic Using A Pulsed Sagnac Interferometer Switch

Abstract: The use of a new Sagnac interferometer switch (SIS) to perform digital optical logic is described. The optical logic switch consists of a Sagnac interferometer with an optical nonlinear material in its loop. Both the SIS input and output logic variables are optical pulses. The output SIS state is a function of the initial mirror alignment and the state of the inducing light beam. Using various SIS interconnections, all 16 two-variable binary logic functions can be implemented. Parallel logic processing of different logic functions can be performed using a single Sagnac interferometer. Since SIS elements are cascadable, sequential operation is also possible. As an example, an implementation of the SIS optical binary full adder is illustrated. If one input is a cw analog signal and another input is an ultrafast optical pulse train, the SIS can also be used as an ultrafast optical sampling device. Conditions for proper optical sampling frequency are presented.

Radio communication system

Abstract: PURPOSE:To improve the output characteristic of a voice band by retarding >=1 demodulated outputs among demodulated outputs of a fixed radio station, giving a prescribed delay time to >=1 output and adding the demodulated outputs. CONSTITUTION:After a demodulated output of a radio station 20 is retarded by a prescribed time by a delay circuit 40 retarding a demodulated output of the fixed radio station 20 by the prescribed time via a transmission line Q2 in a centralized monitor station 30, the result is inputted to an adder circuit 35. In increasing the delay time, the number of zeros and maximum points in the voice band is increased and it is possible to extract frequency components required as minimum for the understanding of a voice. The added output covers the entire voice bands. Thus, the articulation of the voice is improved remarkably.

Delta/sigma type a/d converter

Abstract: PURPOSE: To limit the range of the output amplitude of an integrator, to improve the S/N characteristic of an output from the integrator and to give a margin to an integration characteristic by providing adders adding an input signal to an integration signal, apperantly integrating the input signal and permitting the integrator to simultaneously integrate the input and feedback. CONSTITUTION: When the input signal Vin is given to the adders 90 and 91, the adder 90 takes the difference between the input signal and a feedback signal from an encoder 94, and the integrator 91 integrates the difference. The output of the integrator 91 is given to the other adder 92. It addes the output of the integrator 91 and the input signal Vin, and gives the added output to a quantizer 93. It decides (quantizes) the polarity of the output of the adder 92, outputs a binary output signal Do corresponding to the polarity, and simultaneously gives said signal to a decoder 94. It decodes the output signal of the quantizer 93 to an analog signal, generates the feedback signal, and negatively feeds back said signal to the adder 90. Namely, the adder 92 adds the input signal Vin and the output of the integrator 91, which is apperantly equal to the integration of the input signal Vin. COPYRIGHT: (C)1988,JPO&Japio

Vector multiplier having parallel carry save adder trees

Abstract: High and low order bit carry propagation adders are connected to outputs of carry save adder trees which produce half-sums and half-carries. Following carry propagation addition of the low order bits carry propagation addition of the high order bits is carried out. A carry from the low order bit carry propagation addition is added to the high order bit carry propagation addtion.

Frequency band dividing and encoding system

Abstract: PURPOSE: To improve an S/N and to efficiently encode an input signal by providing a bit distribution decision circuit deciding on the way that bits are distributed to plural channels. CONSTITUTION: A signal inputted from a terminal 1 is inputted to an HPF 21 and an LPF 22, both of which have a frequency a quanter a sampling frequency as an interruption frequency. According to the numbers bn and bl of bits quantized from the bit distribution decision circuit 51, applicable differential PCM encoder circuits 25 and 26 encode outputs from the HPF 21 and the LPF 22. Codes outputted from the encoders 25 and 26 are multiplexed 27 and transmitted from a terminal 7. According to the numbers bn and bl of bits quantized from the bit distribution decision circuit 61, applicable differential PCM decoder circuits 33 and 34 on a decoding side decode code signals received through a terminal 8. An HPF 37 and an LPF 38 extract the high and low frequency components of sampling signals that the circuits 33 and 34 encode, and an adder 39 adds them, thereby obtaining the decoded signal from the signal applied to the terminal 1. Thus the S/N can be improved. COPYRIGHT: (C)1988,JPO&Japio

An NMOS 64b floating-point chip set

Abstract: Three floating point arithmetic chips have been developed in a 1.5μm NMOS process. They are an adder, modified Wallace Tree multiplier, and a combinatorial divider. Speed of scalar operation is 490ns, 660ns and 1610ns, respectively.

Counter-based simulated target generator

Abstract: Apparatus and a method for generating simulated target signals for testing a radar system is disclosed. The fundamental timing intervals for each pulse of the simulated target signal are generated based upon the contents of a high-speed continuously running digital counter. The resolution of the system is determined by the clock rate utilized to increment the counter. Simulated target signals are generated by utilizing an adder to add the desired range to the contents of the counter at a time interval corresponding to each pulse of the radar sync signal. The output signal of the adder corresponds to the expected output of the counter at a time corresponding to the return pulse associated with the transmit sync signal. These values are stored in a digital memory at sequential address locations. The stored values are sequentially read to produce at the output of the memory a digital signal corresponding to the value of the high-speed counter at the time that the return pulse is to be generated. The output data of the memory is compared to the contents of the counter and when they are found to be equal, a pulse of the simulated target signal is generated and the read address to the memory is incremented one count. This process is repeated for each pulse of the transmit sync signal to generate at the output a pulse train with each pulse of the output being delayed from its corresponding pulse of the transmit sync signal by the value determined by the range signal.

SCAPE: a single-chip array processing element for signal and image processing

Abstract: The SCAPE chip is a practical implementation of a VLSI associative string processor; integrating a string of 256 identical processing elements, each comprising 37 bits of content-addressable memory, a 1-bit adder and logic for communication with other processing elements. Packing 143K transistors on a 73 mm2 silicon die, with 2.5 ?m p-well (two-layer metal) CMOS design rules, the SCAPE chip is packaged in a 68-pin chip carrier and, operating at 10 MHz, dissipates less than 900 mW. The paper describes the SCAPE chip architecture and floor plan in structural detail. Testability considerations, design verification and SCAPE software are discussed, and the results from recent performance simulation studies are also reported. The SCAPE chip is scheduled for fabrication, by Plessey (Caswell), in the second quarter of 1986.

Parallel multiplier with a modified booth algorithm

Abstract: A parallel multiplicator including adder circuits based on Booth's algorithm is disclosed. All of the adders of a plurality of rows are constructed based on the carry save system. When the negative partial-product signal is input, the "2's complement" generating signals CB0 to CB3 for the LSB of the negative partial-product signal are input to the bit adder in the lowest order row which corresponds to the LSB of the negative partial-product signal.

Efficient modular design of TSC checkers for M-out-of-2M codes

Abstract: A new design method of TSC m-out-of-2m code checkers is presented. The design is composed basically of two full-adder/half-adder trees, each summing-up the one's of m input lines, and a k-variable 2-pair two-rail code tree that compares the outputs of the two adder trees. The only modules used are full-adders, half-adders and two-rail T2. This method is well suited for VLSI MOS implementation and compared to previous methods it results in significant circuit cost reduction and smaller test set, without sacrificing performance. At the same time the proposed design has all added advantages of a modular design.

Pipeline arithmetic adder and multiplier

Abstract: A fast pipeline adder comprising a plurality of registered adder rows. In one embodiment, additions in the pipeline are realized in reclocked half adders. In another embodiment, modified adders are employed which accept two carry inputs and develop two carry outputs. The resulting number of individual cells is reduced to approximately half of those in the prior embodiment. In still another embodiment, switch means are included in each cell to delete the reclocking and in still another embodiment, the adders in the diagonal of the pipeline adder are provided with additional inputs to permit use of the pipeline adder in recursive addition applications. In still another embodiment, the cells are permitted to output the inverse of the intended signal, reducing thereby the physical realization of the cells and increasing the speed of the cells.