Showing papers on "Adder published in 1991"

Vector processor which can be formed by an integrated circuit of a small size

Abstract: In a vector calculation unit (31), a multiplication and an addition result register (50 and 53) are connected to a pipeline multiplier (14) and a pipeline adder (15), respectively. A multiplication and an addition result bus (52 and 55) are connected to the multiplication and the addition result registers, respectively. A selector (S1) connects one of an input bus (11) and the multiplication and the addition result buses to the first operand register to which a first multiplication and a first addition operand bus (44 and 45') are connected. A selector (S2) connects one of another input bus (12) and the multiplication and the addition result buses to the second operand register to which second multiplication and second addition operand buses (48 and 49) are connected. A selector (S3) connects one of the first multiplication operand, the multiplication result, and the addition result buses to an input of the multiplier. A selector (S4) connects one of the second multiplication operand, the multiplication result, and the addition result buses to another input of the multiplier. A selector (S5) connects one of the first addition operand, the multiplication result, and the addition result buses to an input of the adder. A selector (S6) connects one of the second addition operand, the multiplication result, and the addition result buses to another input of the adder. A selector (S7) connects one of the first addition operand, the second addition operand, the multiplication result, and the addition result buses to an output bus (13).

Carry-save architectures for high-speed digital signal processing

Abstract: Carry-save arithmetic, well known from multiplier architectures, can be used for the efficient CMOS implementation of a much wider variety of algorithms for high-speed digital signal processing than, only multiplication. Existing architectural strategies and circuit concepts for the realization of inner-product based and recursive algorithms are recalled. The two's complement overflow behavior of carry-save arithmetic is analyzed and efficient overflow correction schemes are given. Efficient approaches are presented for the carry-save, implementation of a saturation control. The concepts are extended and refined for the high-throughput implementation of decisiondirected algorithms such as division, modulo multiplication and CORDIC which have yet been avoided because of a lack of efficient concepts for implementation.

A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology

Abstract: A 54 b*54 b multiplier fabricated in a double-metal 0.5 mu m CMOS technology is described. The 54 b*54 b full array is adopted to complete multiplication within one latency. A 10 ns multiplication time is achieved by optimizing both the propagation time of the part consisting of 4-2 compressors and the propagation time of the final adder part. The n-channel pass-transistor circuit and the p-channel load circuit are used at the critical blocks to improve the multiplication speed. This multiplier is intended to be applied to double-precision floating-point data processing based on the IEEE standard up to clock range of 100 MHz. >

High-speed multiplier design using multi-input counter and compressor circuits

Abstract: Multiplication represents one of the major bottlenecks in most digital processing systems Depending on the wordsize, several partial products are added to evaluate the product The well-known shift-and-add algorithm uses minimal hardware but has unacceptable performance for most applications Several parallel fast multiplication schemes have been suggested using several levels of blocks containing full adders This paper presents the design of a fast multiplier implemented using either (7,3) parallel counter or (7:3) compressor circuits for implementation in CMOS technology, The resulting 16 by 16-bit multiplier has less delay than conventional fast multipliers, although the gate count is about 10% higher

Phase-locked loop and resulting frequency multiplier

Abstract: The frequency multiplier 20 is embodied by a phase-locked loop including a phase comparator 11 for commanding a plurality of delay elements 130 to 137 that furnish successive phase-shifted signals CL0-CL7 to a logical adder 16 made up of EXCLUSIVE OR gates.

Maximum likelihood sequence detector

Abstract: A maximum likelihood detector using the Viterbi algorithm for estimating a sequence of data bits received over a communication channel. Depending on the constraint length (C), a plurality of different states is associated with the transmitted bits (e.g. 16 if C=4). The detector comprises various data sources relating respectively to state transition probabilities (branch metrics, previous partial path metrics) and observed values of the received bits. Means are provided for calculating the partial path metrics for each state using values from said data sources. The calculating means comprise a common adder/accumulator for performing repeated additive arithmetic operations and for storing the cumulative result thereof. Multiplexing means are also provided for selectively coupling the data sources in a predetermined order to the adder/accumulator to implement the partial path metric calculation. The architecture is compatible with VLSI techniques and enables the detector to be implemented using minimal semiconductor area. The detector may be used independently as an equaliser or a decoder but in a preferred embodiment both these functions re-use the same common hardware in series enabling both the equaliser and decoder to be implemented in a single integrated circuit (i.e. on one `chip`).

Margins and yield in single flux quantum logic

Abstract: Simulations are used to optimize the design of simple rapid single flux quantum (RSFQ) logic gates and to determine their margins. Optimizations based on maximizing the smallest (critical) margin result in critical margins in the range of 19-50%. A Monte Carlo approach is used to illustrate the relationship between margins and process yield. Based on single gate simulations, the results show that 1 sigma parameter spreads of less than about +or-5% will be required to make medium- or large-scale integrated RSFQ logic circuits. A single-bit full adder using five RSFQ gates and a local self-timing network are simulated with discrete components. The full adder used 2000-A/cm/sup 2/ junctions with a specific capacitance of 0.04 pF/ mu /sup 2/ and had a logic delay of 87 ps and a worst-case margin of +or-19%. A small margin reduction which is not present in the individual gate simulations results from loading. >

Synchronous digital detection of position error signal

Abstract: A sample data position error signal detection means. This invention has application in a digital servo in a magnetic media disk drive environment. In particular, the invention relates to the detection in digital form of position error signals (PES) representative of magnitude and sign of recording head displacement from a track center line. The circuits disclosed provide a digital representation of PES suitable for direct application to a digital signal processor which controls overall servo positioning operations. The invention detects the PES by employing a digital integrator which comprises a register and adder. The composite servo data is first amplified by variable gain amplifier and then undergoes low pass filtering before being digitized by an analog to digital converter (ADC). The digital integration is performed by accumulating a constant number of ADC samples in the register. Before being accumulated in the register, the sampled servo data is alternately multiplied by plus or minus one, using an exclusive-OR gate cascade interposed between the ADC output and adder input. The multiplication of the sampled servo data by plus one or minus one is required for synchronous rectification. Upon completion of accumulation of a prescribed number of ADC samples, the contents of the register are transferred to a temporary buffer pending interrogation by the servo controlled digital signal processor.

Is redundancy necessary to reduce delay

Abstract: The question of whether single stuck-at-fault redundancies are necessary to increase performance or whether they are only an unnecessary by-product of performance optimization is addressed. A constructive resolution of this question is given in the form of an algorithm that takes as input a combinational circuit and returns an irredundant circuit that is as fast. The utility of this algorithm is demonstrated on a well-known circuit, the carry-skip adder, and a novel irredundant design of that adder is presented. As the algorithm may either increase or decrease circuit area, the authors leave unresolved the question as to whether every circuit has an irredundant circuit that is at least as fast and is of equal or lesser area. >

Design of residue generators and multioperand modular adders using carry-save adders

Abstract: The design of residue generators and multioperand modular adders is studied. Novel highly parallel schemes using carry-save adders with end-around carry are proposed for either type of circuit. They are derived on the basis of the periodicity of the series of powers of two taken modulo A (A is a module). The novel circuits are faster and use less hardware than existing similar circuits. >

Echo canceler having adaptive digital filter unit associated with delta-sigma modulation circuit

Abstract: An echo canceler comprises an adaptive digital filter circuit for producing an echo replica signal on the basis of a transmit digital signal and a first digital signal indicative of a far-end signal, and an adder for eliminating the echo signal from a received signal with reference to the echo replica signal, wherein the echo replica signal is modulated by a delta-sigma modulation circuit and, thereafter, converted into an analog signal for allowing the adder to operate on the echo replica signal and the received signal both in an analog form so that the adder with a narrow dynamic range can be available.

Method and apparatus for graphics data interpolation

Abstract: Special purpose graphics instructions are provided to implement linear interpolation of pixel attributes such as a distance (Z) value or color intensity. Multiple fixed-point real number additions are performed in parallel in a 64-bit adder. The real number sums are truncated upon being loaded in a MERGE register, the contents of which are then shifted. By performing two or more of such instructions consecutively, multiple interpolated values are accumulated in the MERGE register.

Digital signal processor with conditional branch decision unit and storage of conditional branch decision results

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

Method and apparatus for data encryption or decryption

Abstract: A cryptographic apparatus comprises a linear feedback shift register for providing a pseudo-random code, coupled to a ciphering device, which is in turn coupled to an adder. The ciphering device encrypts the pseudo-random code. One adder circuit input is coupled to a ciphering device, and the other adder circuit input is coupled to the data input. The adder circuit adds data input signals to ciphering device signals to provide output signals. A method for operation of a ciphering engine is described comprising the steps of providing a random number and setting tap weights for a linear feedback shift register, obtaining a pseudo-random bit stream therefrom, and then encrypting the pseudo-random bit stream to generating a traffic key stream. The traffic key stream is added to a data stream to produce encrypted data from plain-text data or, alternatively, the traffic key stream is added to an encrypted data stream to produce plain-text data.

Performance enhancement through the generalized bypass transform

Abstract: The authors introduce a novel method for the acceleration of general logic circuits based on the assumption that the delay of a circuit is its longest sensitizable (non-false) path. Hence, circuits are accelerated not by reducing path length but by making paths false. The method is based on generalizing the transformation used to obtain the bypass adder to automatically, in an area efficient way, reduce the delay of any combinational logic circuit with paths of varying length. The authors prove that a circuit realizing any function can be accelerated in this manner, give a general algorithm, and prove bounds on the size of the gain expected. >

Multiplexed sigma-delta A/D converter

Abstract: A sigma-delta analog-to-digital converter employs multiplexed single-loop modulators (101, 102, 103, 104) in parallel and respectively phased time-divided clocks. The parallel modulators have the effect of producing digital output at a high sampling frequency that is a multiple of the phased switching frequencies applied to the modulator circuits. In one preferred embodiment, four second-order sigma-delta modulators are driven in clocked phased sequence and combined by a multiplexor circuit. Another embodiment employs second-order modulators using RC integrators. A further embodiment replaces the multiplexor with an adder when in-phase modulator clocks are used, and the adder also acts as a simple low pass filter.

Floating point data processing apparatus which simultaneously effects summation and rounding computations

Abstract: A data processing apparatus and method for floating point data used in a central processing unit for a digital computer effects the four fundamental arithmetic computations of floating point data and the rounding and normalizing computations. In the case of the floating point addition or subtraction, the mantissa portion of the two floating point data and a generated round addition value are summed using a single adder and, in the case of multiplication, a sum output and a carry output of a multiplying unit and a generated round addition value are added using a single adder, so as to correct the least significant bit of the output of the adder or the round addition value is again added. Since the need of effecting readdition for rounding is small, the average processing step numbers becomes small in comparison with the conventional techniques, and, since the mantissa operation and rounding are effected using the same adder at the same time, less hardware is required.

Bus apparatus having hold registers for parallel processing in a microprocessor

Abstract: In a microprocessor having a floating-point execution unit, a floating-point bus control apparatus for performing dual-operation instructions includes a multiplier unit having first and second multiplexed operand inputs, an adder unit also having first and second multiplexed operand inputs, a register for storing real and imaginary components of a constant, another register for storing an intermediate result of the multiplier unit and appropriate interconnections. The floating-point unit of the processor supplies first and second instruction source operands and a destination floating-point register. Multiplexers are used to select which operands are to be input to the appropriate operand inputs so as to implement the corresponding dual-operation algorithm.

New elements of the RSFQ logic family

Abstract: In this report, new rapid single-flux quantum (RSFQ) elements (OR-AND, NOR-AND, half adder, multiplexer, demultiplexer, and shift registers) are presented Operation of these gates has been studied with the help of the personal superconductor circuit analyzer (PSCAN) within the standard RSJ model of Josephson junctions Parameter margins and other performance limits of the new elements are thoroughly investigated

Address control and generating system for digital signal-processor

Abstract: A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage

Bit-level systolic arrays for modular multiplication

Abstract: This paper presents bit-level cellular arrays implementing Blakley's algorithm for multiplication of twon-bit integers modulo anothern-bit integer. The semi-systolic version uses 3n(n+3) single-bit carry save adders and 2n copies of 3-bit carry look-ahead logic, and computes a pair of binary numbers (C, S) in 3n clock cycles such thatC+S?[0, 2N). The carry look-ahead logic is used to estimate the sign of the partial product, which is needed during the reduction process. The final result in the correct range [0,N) can easily be obtained by computingC+S andC+S?N, and selecting the latter if it is positive; otherwise, the former is selected. We construct a localized process dependence graph of this algorithm, and introduce a systolic array containing 3nw simple adder cells. The latency of the systolic array is 6n+w?2, wherew=?n/2?. The systolic version does not require broadcast and can be used to efficiently compute several modular multiplications in a pipelined fashion, producing a result in every clock cycle.

RF coil system for use in magnetic resonance imaging apparatus

Abstract: An RF coil system, used for a magnetic resonance imaging apparatus and adapted to perform at least one of application of an excitation high-frequency magnetic field and detection of magnetic resonance signals, comprises a plurality of coil elements arranged at regularly spaced intervals without overlap therebetween, an RF circuit for putting at least one of the coil elements into an operative state or an inoperative state, a neutralizing circuit for neutralizing inductive coupling between the coil elements, a tuning circuit for tuning at least one of the coil elements to a given frequency, an adder circuit for adding an output signal of the tuning circuit and conductors for electrically connecting the coil elements, the RF circuit, the neutralizing circuit and the adder circuit.

Single chip, mode switchable, matrix multiplier and convolver suitable for color image processing

Abstract: The present invention is an integrated circuit that uses the same coefficient registers, multipliers and adders to perform both matrix multiplication and convolution operations. The multipliers are arranged in columns and rows with the matrix multiplication adders located in the corresponding columns and with the adder for producing the convolution output located in one of the columns. A mode selection switch causes the multiplexers to change input data routing based on the mode selected. The circuit allows loading of all the coefficients or selection of hardwired coefficients. By rerouting the inputs to the multipliers using the multiplexers, the circuit can be easily configured for either mode of operation. The outputs corresponding to the columns are either output directly during matrix multiplication or provided to the convolution adder. The provision of an internal pseudo random number generator, serial inputs and outputs for test data and a signature analysis signal generating circuit allows the circuit to be easily internally tested.

Delay optimization of carry-skip adders and block carry-lookahead adders

Abstract: The worst-case carry propagation delays in carry-skip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. The authors report a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do not guarantee a minimum latency configuration. Under the proposed delay model, critical path delay is calculated taking into account not only the intrinsic gate delays but also the fanin and fanout contributions. >

Electronic arrangement for receiving a modulated carrier signal

Abstract: Electronic receive arrangement for receiving a modulated carrier signal, which arrangement comprises a mixer/demodulator driven with the carrier frequency fc, at least one adder included in a closed signal loop, a low-pass filter, and a pulse shaper constituted by a sigma-delta (one-bit) signal converter and driven with the sampling frequency fs and also comprises a digital decimation filter. The signal loop includes the mixer/demodulator so that the modulated carrier signal is applied to the adder and the output signal of the adder is applied to the mixer/demodulator. The signal loop also comprises a second mixer driven with frequency fc, and the frequencies fs and fc present a common multiple.

Floating point arithmetic unit with size efficient pipelined multiply-add architecture

Abstract: An architecture and method relating to a floating point operation which performs the mathematical computation of A*B+C. The multiplication is accomplished in two or more stages, each stage involving corresponding sets of partial products and concurrently accomplished incremental summations. A pipelined architecture provides for the summation of the least significant bits of an intermediate product with operand C at a stage preceding entry into a full adder. Thereby, a significant portion of the full adder can be replaced by a simpler and smaller incrementer circuit. Partitioning of the multiplication operation into two or more partial product operations proportionally reduces the size of the multiplier required. Pipelining and concurrence execution of multiplication and addition operation in the multiplier provides in two cycles the results of the mathematical operation A*B+C while using a full adder of three-quarters normal size.

Layout efficient 32-bit shifter/register with 16-bit interface

Abstract: An integrated circuit processor architecture that implements digital signal processing (DSP) functions with less hardware, improved speed and a more efficient layout. The central processing unit (CPU) resources are used in conjunction with an integrated multiply/accumulate unit to perform DSP operations. Use of the CPU's internal register for the circular buffer of the DSP multiply/accumulate function allows a minimum amount of lower speed hardware to be used for the multiply/accumulate unit and permits DSP operations to be performed in parallel. The multiply/accumulate unit takes advantage of the inherent accumulating properties of conventional multiplier designs to perform multiplication of two signed binary numbers using the modified Booth's algorithm but in both reduced cycle time and hardware requirements. This is accomplished by using the adder within the multiplier to sum the product terms. Instead of clearing the adder of the result of one multiplication before beginning another, the result is maintained and all subsequent partial products are added to it to generate a final output. The placement of the 32-bits of the multiply/accumulate unit's multiplicand register is arranged in two rows of 8 even bits and two rows of 8 odd bits to allow left shift by two with a single loop around and to provide direct interface with the 16-bit data latch register on its input and the rest of the 32-bit arithmetic logic unit (ALU) on its output.

Active control precision damping table

Abstract: An active control precision damping table supported by air springs. Level displacement and vibrations of the table are detected by a sensor or sensors, and sensor outputs are fed to a variation adder which carries out an adding operation on one of the sensor outputs and an inversion signal produced by inverting the other sensor output 180 degrees. The adder outputs results of the operation to a drive circuit, which in turn outputs a drive signal to a control valve. The control valve is operable in response to the drive signal to adjust air pressure in pressure vessels of the air springs.