Showing papers on "Adder published in 1992"

A new design of the CMOS full adder

Abstract: By using the transmission function theory, two CMOS full adders are designed, both of which have simpler circuits than the conventional full adder. Computer simulations with SPICE2G5 show that they can realize the expected logic functions and they have desirable transfer characteristics. >

A spanning tree carry lookahead adder

Abstract: The design of the 56-b significant adder used in the Advanced Micro Devices Am29050 microprocessor is described. Originally implemented in a 1- mu m design role CMOS process, it evaluates 56-b sums in well under 4 ns. The adder employs a novel method for combining carries which does not require the back propagation associated with carry lookahead, and is not limited to radix-2 trees, as is the binary lookahead carry tree of R.P. Brent and H.T. Kung (1982). The adder also utilizes a hybrid carry lookahead-carry select structure which reduces the number of carriers that need to be derived in the carry lookahead tree. This approach produces a circuit well suited for CMOS implementation because of its balanced load distribution and regular layout. >

Asynchronous Datapaths and the Design of an Asynchronous Adder

Abstract: This paper presents a general method for designing delay insensitive datapath circuits. Its emphasis is on the formal derivation of a circuit from its specification. We discuss the properties required in a code that is used to transmit data asynchronously, and we introduce such a code. We introduce a general method (in the form of a theorem) for distributing the evaluation of a function over a number of concurrent cells. This method requires that the code be "distributive." We apply the method to the familiar example of a ripple-carry adder, and we give a CMOS implementation of the adder.

M*N Booth encoded multiplier generator using optimized Wallace trees

Abstract: The architecture and the design method for an M-*-N Booth-encoded parallel-multiplier generator are discussed. An algorithm for reducing the delay inside the branches of the Wallace tree section is presented and explained. The final stage of adding two (N+M-1)-bit numbers is done by an optimal carry-select adder stage. An algorithm for optimal partitioning of the (N+M-1)-bit adder is also presented. >

Chemical implementation of finite-state machines

Abstract: With methods developed in a prior article on the chemical kinetic implementation of a McCulloch-Pitts neuron, connections among neurons, logic gates, and a clocking mechanism, we construct examples of clocked finite-state machines. These machines include a binary decoder, a binary adder, and a stack memory. An example of the operation of the binary adder is given, and the chemical concentrations corresponding to the state of each chemical neuron are followed in time. Using these methods, we can, in principle, construct a universal Turing machine, and these chemical networks inherit the halting problem

Dct/idct processor and data processing method

Abstract: A one-dimensional discrete cosine transform processor of N (N: positive integer)-term input data X includes a preprocessing section for carrying out addition and subtraction of (i)th-term data x (i) and (N-i)th-term data x (N-1) of input data X, and a unit for performing a product sum operation for sets of intermediate data subjected to preprocessing by addition and sets of intermediate data subjected to preprocessing by subtraction, respectively. The product sum operation unit includes a data rearranging unit for outputting, in parallel and in order, bit data of the same figure of a set of data, a partial sum generator for generating a partial sum by using the parallel bit data as an address, and an accumulator for accumulating outputs of the partial sum generator. A one-dimensional inverse discrete cosine transform processor of N-term input data X includes a unit for performing a product sum operation of input data, and a postprocessing section for carrying out addition and subtraction of 2-term data in a predetermined combination of an output of the product sum operation unit. The number of times of multiplication is reduced by utilizing inherent characteristics of coefficients of DCT/IDCT processing. Since the product sum operation is performed by a ROM table and an adder, a faster multiplication is realized.

Fast and flexible architectures for RNS arithmetic decoding

Abstract: An implementation of a fast and flexible residue decoder for residue-number-system (RNS)-based architectures is proposed. The decoder is based on the Chinese remainder theorem. It decodes a set of residues to its equivalent representation in weighted binary number system. This decoder is flexible since the decoded data can be selected to be either unsigned magnitude or 2's complement binary number. Two different architectures are analyzed; the first one is based on using carry-save adders, while the other is based on utilizing modulo adders. The implementation of both architectures is modular and is based on simple cells, which leads to efficient VLSI realization. The proposed decoder is fast; it has a time complexity of theta (log N), where N is the number of moduli. >

Circuit and method for cancelling nonlinearity error associated with component value mismatches in a data converter

Abstract: A circuit (10) and method for minimizing nonlinearity errors in an oversampled data converter (40) resulting from errors in the intended values of components (42-49) of the converter (40). An adder section (11) is used to add a digital input sample to a previously existing sum generated from an immediately preceding digital input sample. A resulting sum is converter from binary code to thermometer code by an encoder (20). Combinatorial logic (24) is used to provide control signals for controlling switching of the components in a manner which both converts the nonlinearity error to a noise error and frequency shifts the noise error out of a frequency passband of the converter to higher frequencies where the error is subsequently filtered.

A fast VLSI adder architecture

Abstract: An architecture for performing fixed-point, high-speed, two's-complement, bit-parallel addition by using the carry-free property of redundant arithmetic and a fast parallel redundant-to-binary conversion scheme is presented. The internal numbers are represented in radix-2 redundant digit form, and the inputs and the output of the adder are represented in two's-complement binary form. The adder operands are added first in a radix-2 redundant adder to produce the result in radix-2 digit (-1, 0, 1) form. This result is converted to two's-complement binary form using the parallel conversion scheme. The high-speed conversion for long words is achieved through the use of a novel sign-select operation. The proposed adder, referred to as the sign-select conversion adder, is faster than all previous high-speed two's-complement binary adders for large word lengths. The implementation is highly regular with repeated modules and is very well suited for VLSI implementation. >

Apparatus and method for performing speech rate modification and improved fidelity

Abstract: In a speech rate modification system and method, correlation functions between different segments of input speech signal are computed by a correlator (17), the amplitude of the input signal is controlled by two multipliers (19, 20) which multiply the input speech signal by an increasing window function and by a decreasing window function, or vice versa, respectively, produced by a window function generator (18), and then output signals of the multipliers (19, 20) are added to each other by an adder (21) at such a relative delay within one unitary segment (T) as to maximize the value of the correlation function, and the input voice signal and the output of the adder (21) are selected by a multiplier (22), to be issued as a rate-modified speech signal.

Viterbi detector having adjustable detection thresholds for PRML class IV sampling data detection

Abstract: A Viterbi detector for a PR4,ML data channel includes a data sample input for receiving digital data samples from a source. Digital data samples are taken of data which has been coded in a predetermined data code format and which has been passed through a data degrading channel. A delay circuit delays the digital data samples received at the data sample input. A delay selector controls an output of the delay circuit in accordance with a feedback control bit value. An adder circuit combines data samples from the data sample input with delayed samples from the delay circuit to produce a sum. A threshold input receives programmable positive and negative data threshold values. A threshold selector puts out either the positive or the negative threshold values in accordance with a sign bit control value. A comparator compares the sum with a selected threshold value and puts out a logical value based upon comparison thereof. It includes Viterbi decision state logic for determining the sign bit control value, the feedback control bit value, and two raw data bits for each incoming data sample. A memory path circuit decodes a sequence of consecutive values of the raw data bits in accordance with a predetermined maximum likelihood trellis decode logic table related to the predetermined data code format and puts out a sequence of detected code bits.

Synthesis techniques for CMOS folded source-coupled logic circuits

Abstract: The application of series-gated, multiplexer-minimization, and variable-entered mapping methods to the synthesis of fully differential CMOS folded source-coupled logic (FSCL) gates is described. In contrast to conventional static logic, FSCL dissipates DC power. Its total power consumption is competitive at higher speeds where its low digital switching noise is most advantageous. The minimum propagation delay of a simple FSCL gate compares favorably to a conventional gate. Complex functions are generally faster in FSCL since its fully differential topology requires fewer stages of delay. Simulated and measured results are presented for several combinational and sequential FSCL gates in a 2- mu m p-well CMOS process. With V/sub dd/=5 V, a FSCL (static) inverter achieved a minimum propagation delay of 400 ps (350 ps) with a power-delay product of 0.5 pJ (0.3 pJ); a FSCL (static) 1-b full adder achieved a minimum delay of 3.0 ns (12.0 ns) with a power-delay product of 0.3 pJ (11.0 pJ). >

Delay optimization of carry-skip adders and block carry-lookahead adders using multidimensional dynamic programming

Abstract: The worst-case carry propagation delays in carry-skip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. The authors report on a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do not guarantee a minimum latency configuration. Under the delay model, critical path delay is calculated not only taking into account the intrinsic gate delays, but also the fanin and fanout contributions. >

VLSI implementation of residue adders based on binary adders

Abstract: The implementation of residue number system (RNS) adders based on binary adders is described. These adders use two cycles of addition and support any class of modulus. A technique for choosing the correct sum in a two-cycle residue addition is presented and proved correct. Three VLSI layout approaches for residue adders are described and performance figures for area and speed are given. The two approaches using one binary adder offer savings of about 30% in area and significant improvement in speed/area product over the approach using two binary adders. >

High-speed addition in CMOS

Abstract: A fully static complementary metal-oxide semiconductor (CMOS) implementation of a Ling-type 32-bit adder is described. The implementation saves up to one gate delay and always reduces the number of serial transistors in the worst-case critical path over the conventional carry look-ahead (CLA) approach with a negligible increaser in hardware. >

New memoryless, mod (2n±1) residue multiplier

Abstract: A mod (2n±1) residue multiplier is introduced This multiplier does not use any memory Using VLSI components, a very high speed multiplier is achieved The whole implementation consists of a binary multiplier, adder and a few logic gates This implies a reduced hardware requirement

Method and system for a multi channel and search global position signal processor

Abstract: There is disclosed a multi channel GPS digital signal processor on a single IC. Each channel contains circuitry to process L1 or L2 P(Y) and C/A-code signals. In addition a search processor is included to achieve fast signal acquisition. Low power adder/accumulators have been designed to provide for a high precision digital oscillator whose output is synchronous to a high speed clock. The IC contains a full low power null detector and eight correlators to aid in signal acquisition.

On-the-fly rounding (computing arithmetic)

Abstract: In implementations of operations based on digit-recurrence algorithms such as division, left-to-right multiplication and square root, the result is obtained in digit-serial form, from most significant digit to least significant. To reduce the complexity of the result-digit selection and allow the use of redundant addition, the result-digit has values from a signed-digit set. As a consequence, the result has to be converted to conventional representation, which can be done on-the-fly as the digits are produced, without the use of a carry-propagate adder. The authors describe three ways to modify this conversion process so that the result is rounded. The resulting operation is fast because no carry-propagate addition is needed. The schemes described apply also to online arithmetic operations. >

Canonical signed two's complement constant multiplier compiler

Abstract: A constant multiplier compiler model allows a modified canonical signed two's complement constant multiplier circuit design to be generated from a user specification of the desired constant. A netlist of a modified canonical signed two's complement constant multiplier circuit for computing a product of a multi-bit multiplicand and a multi-bit constant is automatically generated by modifying a netlist of a precursor signed two's complement constant multiplier circuit for computing a product of the multi-bit multiplicand and a multi-bit constant that is all ones. The number of zeros in the multi-bit constant is first maximized by converting the constant to modified canonical form. Then, for each zero in the multi-bit constant, a corresponding logical column of full adders is deleted and each output signal of each adder so deleted is logically connected to a corresponding output signal in a preceding logical column of adders. Two exceptions to the foregoing rule occur. In the case of a first logical column of adders having no preceding logical column of adders, each output signal of each adder deleted is logically connected to a bit of the multi-bit multiplicand. In the case of a logical row of adders receiving a most significant bit of the multi-bit multiplicand, each output signal of each adder deleted is logically connected to one of the most significant bit of the multi-bit multiplicand and logic zero. The method produces a minimum layout, minimizing silicon cost, and produces a high performance design with critical paths optimized in terms of time delay.

Novel approaches to the design of VLSI RNS multipliers

Abstract: Two approaches are proposed for the design of a fast residue number-based multiplier over a Galois field GF(p), where p is a prime number. The first approach uses an isomorphic mapping from the additive index group, modulo (p-1), of GF(p) onto the direct sum of a set of submodular additive groups. The submoduli are selected for minimizing the hardware and increasing the speed. This is accomplished by fully exploiting the properties of a Galois field. The second one uses symmetric residue number arithmetic to perform multiplication. This uses a pseudoprimitive root as the generator for the elements of the multiplicative group of GF(p) and reduces the index storage hardware by 50% and the adder hardware by 1 bit. Multipliers designed with these approaches would be faster and use less silicon area compared to earlier designs reported in the literature. >

Horizontal magnetoresistive head apparatus and method for detecting magnetic data

Abstract: An apparatus and method for detecting magnetic data on media is disclosed which utilizes an array or arrays of horizontal magnetoresistive sensors. The present invention detects the pitch or separation of magnetic transition data on the magnetic medium under test, and generates a signal that is independent of the velocity of the medium. In one embodiment, the magnetoresistive sensors employed in an array are spaced apart a distance which corresponds to the separation of magnetic transition data of interest, and the output of each sensor is connected to a voltage adder. The signal from the voltage adder is at a maximum when the separation of the magnetic transition data corresponds to the sensor separation. A comparator is connected to the output of the voltage adder, and compares the voltage adder output to a predetermined threshold voltage before indicating that a medium having a particular magnetic transition data pattern is detected. Alternate embodiments contemplate connecting linear circuitry, digital circuitry, fuzzy logic or other electronic circuitry to the array of magnetoresistive sensors. An apparatus according to the present invention is accurate, requires a minimum of parts, is simple and inexpensive to manufacture, and may be employed in a currency validator, magnetic card reader or the like.

Time redundant error correcting adders and multipliers

Abstract: Time redundancy is an approach to achieve fault-tolerance without introducing too much hardware overhead and can be used in applications where time is not critical. The basic REcomputing with Duplication With Comparison error-detecting adder proposed by Johnson is extended to perform error correction. Time redundant multipliers that can detect and correct errors are also proposed in this paper. The hardware overhead of time redundant error correcting adders and multipliers is much lower than that of hardware or information redundancy approaches. Hence they are useful in systems where hardware complexity is the primary concern. >

Edge-valued binary decision for multi-level hierarchical verification

Abstract: The authors present a new data structure called edge-valued binary decision diagrams (EVs) as a representation of functions. An EV is an extension of ordered binary decision diagrams that allows for multilevel and hierarchical verification. It is shown that an EV is a compact and canonical representation for arbitrary integer functions. Hence, the specification can be at a higher level than the implementation. The variable ordering strategy for an EV can be derived from a higher-level functional specification instead of the gate-level specification. Examples of the design of a 64-b comparator and of a 64-b ripple-carry adder are included. >

Squaring circuit for binary numbers

Abstract: The present invention relates to a squaring circuit for a binary number X of n bits x0 to xn-1, comprising: a table (20) of the squares of numbers p consisting of bits x1 to xn-2; an adder of numbers of 2n-3 bits (ADD) receiving, on a first input, a number constituted by the bit xn-1, juxtaposed to the left of the square p supplied by the table; a first routing means (&2... n a second routing means (n a AND gate (&n) linked to the remaining line of the second input and receiving at its input the bits x0 and xn-1. The square X of the number X consists of the output of the adder, with which are juxtaposed to the right one bit at 0 and the bit x0.

An efficient redundant-binary number to binary number converter

Abstract: The authors present a method for converting the redundant-binary representation into the 2's complement binary representation. Instead of using the conventional full adders, a more efficient redundant-binary number to binary number converter can be designed with the aid of the new variable C/sub i/. The method can be applied to both 'serial' and 'lookahead' modes. In both modes, it was shown that the authors' converter takes less chip area and conversion time when compared with the conventional method. >

'Overturned-stairs' adder trees and multiplier design

Abstract: Wallace trees are the theoretically fastest multioperand adders. However, their complex interconnections do not permit practical implementations. A family of Overturned-Stairs trees which achieve the same speed performance as equivalent Wallace trees in many cases, but require a simple and regular interconnection scheme is introduced. These trees can be designed in a systematic way and laid out regularly in a VLSI circuit. A comparison is made between various trees to provide useful indexes for a practical design. The design of a 16*16 2's complement parallel multiplier using Overturned-Stairs trees is studied as an illustration. >

Equalizer for data receiver apparatus

Abstract: In an equalizer including a plurality of delay elements, a plurality of weighting elements and an adder, the impulse response of a signal transmission channel is estimated to selectively switch over a plurality of selector switches associated with the inputs and outputs of the respective delay elements, thereby selectively changing the combination of the delay elements and the weighting elements transmitting an input signal from the channel to the adder and also changing the combination of the adder and a delay element feeding back the output of the discriminator to the adder. Thus, the number of required taps of the equalizer can be reduced, so that the power consumption and size of the equalizer can be reduced.

Flexible N-way memory interleaving

Abstract: The invention comprises methods and apparatuses for interleaving a number of memory cards of different sizes. A restricted range modulo-N adder for identifying and selecting the correct interleave card is provided. Another aspect of the invention provides a computer system with flexible memory interleaving capability.

Concurrent error detection in ALUs by recomputing with rotated operands

Abstract: Analyzes concurrent error detection in arithmetic logic units by recomputing with rotated operands by k bits (RERO-k). Even though RERO-k was suggested as an extension of recomputation with shifted operands by k bits (RESO-k), the RERO implementation for arithmetic operations and its application to carry lookahead adders have not been shown. It is claimed that complex control units should be used to make RERO feasible. This control hardware may add additional faults which are different from the bit-slice faults in the ALU. In this approach, by adding only one spare bit slice in the arithmetic logic unit, RERO is possible for error detection of logical and arithmetic operations in either ripple carry adders and carry lookahead adders without any additional hardware control unit. Proof will be given that RERO-k can detect (k mod n) consecutive errors in logical operations and (k mod (n+1)-1) consecutive errors in arithmetic operations, where n is the length of the original arithmetic logic unit. This demonstrates that RERO preserves all the error detection features of RESO. With less hardware, time redundancy and more flexibility for error detection, the approach makes RERO more appropriate for VLSI designs. >