Showing papers on "Adder published in 2008"

Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Tunnel Junctions

Abstract: Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. We have fabricated a nonvolatile full adder based on logic-in-memory architecture using magnetic tunnel junctions (MTJs) in combination with metal oxide semiconductor (MOS) transistors. Magnesium oxide (MgO) barrier MTJs are used to take advantage of their high tunnel magneto-resistance (TMR) ratio and spin-injection write capability. The MOS transistors are fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The basic operation of the full adder is confirmed.

Variable latency speculative addition: a new paradigm for arithmetic circuit design

Abstract: Adders are one of the key components in arithmetic circuits. Enhancing their performance can significantly improve the quality of arithmetic designs. This is the reason why the theoretical lower bounds on the delay and area of an adder have been analysed, and circuits with performance close to these bounds have been designed. In this paper, we present a novel adder design that is exponentially faster than traditional adders; however, it produces incorrect results, deterministically, for a very small fraction of input combinations. We have also constructed a reliable version of this adder that can detect and correct mistakes when they occur. This creates the possibility of a variable-latency adder that produces a correct result very fast with extremely high probability; however, in some rare cases when an error is detected, the correction term must be applied and the correct result is produced after some time. Since errors occur with extremely low probability, this new type of adder is significantly faster than state-of-the-art adders when the overall latency is averaged over many additions.

FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic

Abstract: In this paper, we present the design optimization of one- and two-dimensional fully pipelined computing structures for area-delay-power-efficient implementation of finite-impulse-response (FIR) filter by systolic decomposition of distributed arithmetic (DA)-based inner-product computation. The systolic decomposition scheme is found to offer a flexible choice of the address length of the lookup tables (LUT) for DA-based computation to decide on suitable area time tradeoff. It is observed that by using smaller address lengths for DA-based computing units, it is possible to reduce the memory size, but on the other hand that leads to increase of adder complexity and the latency. For efficient DA-based realization of FIR filters of different orders, the flexible linear systolic design is implemented on a Xilinx Virtex-E XCV2000E FPGA using a hybrid combination of Handel-C and parameterizable VHDL cores. Various key performance metrics such as number of slices, maximum usable frequency, dynamic power consumption, energy density, and energy throughput are estimated for different filter orders and address lengths. Analysis of the results obtained indicate that performance metrics of the proposed implementation is broadly in line with theoretical expectations. It is found that the choice of address length yields the best of area-delay-power-efficient realizations of the FIR filter for various filter orders. Moreover, the proposed FPGA implementation is found to involve significantly less area-delay complexity compared with the existing DA-based implementations of FIR filter.

A Novel Reversible BCD Adder For Nanotechnology Based Systems

Abstract: This paper proposes two reversible logic gates, HNFG and HNG. The first gate HNFG can be used as two Feynman Gates. It is suitable for a single copy of two bits with no garbage outputs. It can be used as "Copying Circuit" to increase fan-out because fan-out is not allowed in reversible circuits. The second gate HNG can implement all Boolean functions. It also can be used to design optimized adder architectures. This paper also proposes a novel reversible full adder. One of the prominent functionalities of the proposed HNG gate is that it can work singly as a reversible full adder unit. The proposed reversible full adder contains only one gate. We show that its hardware complexity is less than the existing reversible full adders. The proposed full adder is then applied to the design of a reversible 4-bit parallel adder. A reversible Binary Coded Decimal (BCD) adder circuit is also proposed. The proposed circuit can add two 4-bit binary variables and it transforms the result into the appropriate BCD number using efficient error correction modules. We show that the proposed reversible BCD adder has lower hardware complexity and it is much better and optimized in terms of number of reversible gates and garbage outputs with compared to the existing counterparts.

Design of a Novel Reversible Multiplier Circuit Using HNG Gate in Nanotechnology

Abstract: Reversible logic circuits are of interests to power minimization having applications in low power CMOS design, optical information processing, DNA computing, bioinformatics, quantum computing and nanotechnology. In this paper we propose a novel 4x4 bit reversible multiplier circuit. The proposed reversible multiplier is faster and has lower hardware complexity compared to the existing counterparts. It is also better than the existing counterparts in term of number of gates, garbage outputs and constant inputs. Haghparast and Navi recently proposed a 4x4 reversible gate called "HNG". The reversible HNG gate can work singly as a reversible full adder. In this paper we use HNG gates to construct the reversible multiplier circuit. The proposed reversible multiplier circuit using HNG gate can multiply two 4-bits binary numbers. The proposed reversible 4x4 multiplier circuit can be generalized for NxN bit multiplication. We can use it to construct more complex systems in nanotechnology.

All-optical half adder based on cross structures in two-dimensional photonic crystals.

Abstract: We propose an all-optical half adder based on two different cross structures in two-dimensional photonic crystals. One cross structure contains nonlinear materials and functions as an "AND" logic gate. The other one only contains linear materials and acts as an "XOR" logic gate. The system is demonstrated numerically by the FDTD method to work as expected. The optimal operating speed without considering the response time of the nonlinear material, the least ON to OFF logic-level contrast ratio, and the minimum power for this half adder obtained were 0.91 Tbps, 16 dB and 436 mW, respectively. The proposed structure has the potential to be used for constructing all-optical integrated digital computing circuits.

A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters

Abstract: The complexity of linear-phase finite-impulse-response (FIR) filters is dominated by the complexity of coefficient multipliers. The number of adders (subtractors) used to implement the multipliers determines the complexity of the FIR filters. It is well known that common subexpression elimination (CSE) methods based on canonical signed digit (CSD) coefficients reduce the number of adders required in the multipliers of FIR filters. A new CSE algorithm using binary representation of coefficients for the implementation of higher order FIR filters with a fewer number of adders than CSD-based CSE methods is presented in this paper. We show that the CSE method is more efficient in reducing the number of adders needed to realize the multipliers when the filter coefficients are represented in the binary form. Our observation is that the number of unpaired bits (bits that do not form CSs) is considerably few for binary coefficients compared to CSD coefficients, particularly for higher order FIR filters. As a result, the proposed binary-coefficient-based CSE method offers good reduction in the number of adders in realizing higher order filters. The reduction of adders is achieved without much increase in critical path length of filter coefficient multipliers. Design examples of FIR filters show that our method offers an average adder reduction of 18% over the best known CSE method, without any increase in the logic depth.

Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell

Abstract: In this paper a new low power and high performance adder cell using a new design style called “Bridge” is proposed. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption, by using some transistors, named bridge transistors. Simulation results illustrate the superiority of the resulting proposed adder against conventional CMOS 1-bit full-adder in terms of power, delay and PDP. We have performed simulations using HSPICE in a 90 nanometer (nm) standard CMOS technology at room temperature; with supply voltage variation from 0.65v to 1.5v with 0.05v steps.

A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates

Abstract: The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15 m and 0.35 m technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE. Keywords—XOR gate, full adder, improvement in speed, area minimization, transistor count minimization.

New VLSI Architecture of Parallel Multiplier-Accumulator Based on Radix-2 Modified Booth Algorithm

Abstract: In this paper, we propose a new architecture of multiplier-and-accumulator (MAC) for high speed multiplication and accumulation arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator which has the largest delay in MAC was removed and its function was included into CSA, the overall performance becomes to be elevated. The proposed CSA tree uses 1's complement-based radix-2 modified booth algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of operands. The CSA propagates the carries by the least significant bits of the partial products and generates the least significant bits in advance for decreasing the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits not the output of the final adder for improving the performance by optimizing the efficiency of pipeline scheme. The proposed architecture was synthesized with and 90nm standard CMOS library after designing it. We analyzed the results such as hardware resource, delay, and pipeline which are based on the theoretical and experimental estimation. We used Sakurai's alpha power low for the delay modeling. The proposed MAC has the superior properties to the standard design in many ways and its performance is twice as much than the previous research in the similar clock frequency.

An FPGA-specific approach to floating-point accumulation and sum-of-products

Abstract: This article studies two common situations where the flexibility of FPGAs allows one to design application-specific floating-point operators which are more efficient and more accurate than those offered by processors and GPUs. First, for applications involving the addition of a large number of floating-point values, an ad-hoc accumulator is proposed. By tailoring its parameters to the numerical requirements of the application, it can be made arbitrarily accurate, at an area cost comparable to that of a standard floating-point adder, and at a higher frequency. The second example is the sum-of-product operation, which is the building block of matrix computations. A novel architecture is proposed that feeds the previous accumulator out of a floating-point multiplier whose rounding logic has been removed, again improving the area/accuracy tradeoff. These architectures are implemented within the FloPoCo generator, freely available under the LGPL.

Novel Reversible Multiplier Circuit in Nanotechnology

Abstract: Reversible computation is of the growing interests to power minimization having applications in low power CMOS design, quantum computing, optical information processing, DNA computing, bioinformatics and nanotechnology. This paper proposes a novel 4x4 bit reversible Multiplier circuit. It is faster and has lower hardware complexity compared to the existing designs. In addition, the proposed reversible multiplier is better than the existing counterparts in term of number of gates and number of garbage outputs. Haghparast and Navi recently proposed a 4x4 reversible gate called "MKG". The reversible MKG gate can work singly as a reversible full adder. In this paper we use MKG gates to construct the reversible multiplier circuit. The proposed reversible multiplier circuit can multiply two 4-bits binary numbers. It can be generalized for NxN bit multiplication.

Photonic Processing for Digital Comparison and Full Addition Based on Semiconductor Optical Amplifiers

Abstract: An N bit all-optical comparator and an all-optical full adder are presented. These complex circuits, which perform photonic digital processing, are implemented cascading a unique basic gate that exploits cross gain modulation and cross-polarization rotation in a single semiconductor optical amplifier (SOA). Since the interacting signals are counterpropagating in the SOA, they can be set at the same wavelength. Photonic processing improves the speed of the optical networks by reducing the packet latency time to the time-of-flight in the nodes. Digital comparison and full-addition are key functionalities for the processing of the packet labels. Integrated realizations are crucial, thus, SOAs represent a suitable mean both because they allow hybrid integrated solutions and fast operation speed. The performances of the basic gate, the comparator, and the full adder are investigated both in terms of bit error rate and eye opening. To the best of our knowledge this is the first time it is reported on the implementation of an all-optical comparator able to compare patterns longer than 1 bit. Previous works demonstrate the comparison of 1 bit patterns. Only few works report on an all-optical full adder implementation, but with different schemes. In our implementation, sum and carry out do not depend directly on the carry in, thus potentially improving the output signal quality when cascading multiple full adders.

Design of a Novel Fault Tolerant Reversible Full Adder for Nanotechnology Based Systems

Abstract: Reversible computation plays an important role in the synthesis of circuits having application in quantum computing, low power CMOS design, bioinformatics and nanotechnology-based systems. Conventional logic circuits are not reversible. A reversible circuit maps each input vector, into a unique output vector and vice versa. We demonstrate how the well-known and very useful, Toffoli gate can be synthesized from only two parity-preserving reversible gates. Parity preserving reversible gates refers to those reversible gates for which the parity of the outputs matches that of the inputs. The proposed parity preserving Toffoli gate renders a wide class of circuit faults readily detectable at the circuit's outputs. It allows any fault that affects no more than a single signal to be detectable at the circuit's primary outputs. We show that our proposed parity-preserving Toffoli gate is much better in terms of number of reversible gates, number of garbage outputs and hardware complexity with compared to the existing counterpart. Then we apply the proposed fault tolerant Toffoli gate to the design of a fault tolerant reversible full adder, which is a versatile and widely used building block in computer arithmetic.

An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design

Abstract: In this paper, an efficient VLSI architecture of a pipeline fast Fourier transform (FFT) processor capable of producing the normal output order sequence is presented. A new FFT design based on the decimated dual-path delay feed-forward data commutator unit by splitting the input stream into two half-word streams is first proposed. The resulting architecture can achieve full hardware efficiency such that the required number of adders can be reduced by half. Next, in order to generate the normal output order sequence, this paper also presents a sequence conversion method by integrating the conversion function into the last-stage data commutator module.

A new high dynamic range moduli set with efficient reverse converter

Abstract: The Residue Number System (RNS) is a representation system which provides fast and parallel arithmetic. It has a wide application in digital signal processing and provides enhanced fault tolerance capabilities. In this work, we consider the 3-moduli set {2^n, 2^2^n-1, 2^2^n+1} and propose its residue to binary converter using the Chinese Remainder Theorem. We present its simple hardware implementation that is mainly composed of one Carry Save Adder (CSA), a 4n bit modulo 2^4^n-1 adder, and a few gates. We compare the performance and area utilization of our reverse converter to the reverse converters of the moduli sets { 2^n-1, 2^n, 2^n+1, 2^2^n+1} and {2^n-1, 2^n, 2^n+1, 2^n-2^(^n^+^1^)^/^2+1, 2^n+2^(^n^+^1^)^/^2+1} that have the same dynamic range and we demonstrate that our reverse converter is better in terms of performance and area utilization.

A floating-point fused add-subtract unit

Abstract: A floating-point fused add-subtract unit is described that performs simultaneous floating-point add and subtract operations on a common pair of single-precision data in about the same time that it takes to perform a single addition with a conventional floating-point adder. When placed and routed in a 45 nm process, the fused add-subtract unit is only about 40% larger than a conventional floating-point adder.

A Re-design Technique for Datapath Modules in Error Tolerant Applications

Abstract: Scaling CMOS into nano-scale is decreasing yields. The concept of error tolerance has been proposed to reverse this trend by developing new test techniques for chips used in many applications, such as audio, video, graphics, games, and error-correcting codes for wireless communication. In such chips, manufacturing defects that induce errors with severities within specified thresholds (determined via analysis of applications) are deemed acceptable. In this paper, we develop an approach to re-design datapath modules to exploit acceptable errors to improve yield. Under the manufacturing yield model (Ym = Ypara * Yfunc), parametric yield (Ypara) improvement due to decrease in delay is more important than functional yield (Yfunc) improvement due to decrease in area. So our re-designing technique mainly focuses on reducing delay of datapath modules to improve parametric yield. In particular, we propose multiple approaches and apply them to improve yield of a wide range of adder architectures by exploiting error tolerance in these applications. Experiment results show that even for small thresholds on error severity, we can obtain significant improvements in manufacturing yield.

Efficient synthesis of compressor trees on FPGAs

Abstract: FPGA performance is currently lacking for arithmetic circuits. Large sums of k > 2 integer values is a computationally intensive operation in applications such as digital signal and video processing. In ASIC design, compressor trees, such as Wallace and Dadda trees, are used for parallel accumulation; however, the LUT structure and fast carry-chains employed by modern FPGAs favor trees of carry-propagate adders (CPAs), which are a poor choice for ASIC design. This paper presents the first method to successfully synthesize compressor trees on LUT-based FPGAs. In particular, we have found that generalized parallel counters (GPCs) map quite well to LUTs on FPGAs; a heuristic, presented within, constructs a compressor tree from a library of GPCs that can efficiently be implemented on the target FPGA. Compared to the ternary adder trees produced by commercial synthesis tools, our heuristic reduces the combinational delay by 27.5%, on average, within a tolerable average area increase of 5.7%.

On the Reliability of Majority Gates Full Adders

Abstract: This paper studies the reliability of three different majority gates full adder (FA) designs, and compares them with that of a standard XOR-based FA. The analysis provides insights into different parameters that affect the reliability of FAs. The probability transfer matrix method is used to exactly calculate the reliability of the FAs under investigation. All simulation results show that majority gates FAs are more robust than a standard XOR-based FA. They also show how different gates affect the FAs' reliabilities and are extrapolated to give reliability estimates from the device level. Such reliability analyses should be used for a better characterization of FA designs for future nanoelectronic technologies, in addition to the well-known speed and power consumption (which have long been used for selecting and ranking FA designs).

Information Theoretic Approach to Complexity Reduction of FIR Filter Design

Abstract: This paper presents a new paradigm of design methodology to reduce the complexity of application-specific finite-impulse response (FIR) digital filters. A new adder graph data structure called the multiroot binary partition graph (MBPG) is proposed for the formulation of the multiple constant multiplication problem of FIR filter design. The set of coefficients in any fixed point representation is partitioned into symbols so that common subexpression identification and elimination become congruent to information parsing for data compression. A minimum number of different pairs or groups of symbols and residues can be used to code a set of coefficients based on their probability and conditional probability of occurrence. This ingenious concept enables the notion of entropy to be applied as a quantitative measure to evaluate the coding density of different compositions of symbols towards a set of coefficients. The minimal vertex set MBPG synthesized by our proposed information theoretic approach results in direct correspondences between the vertices and adders, and edges and physical interconnections. Unlike the common subexpression elimination algorithms based on other graph data structures, the symbol-level information carried in each vertex and the graph isomorphism of MBPG promise further fine-grain optimization in a reduced search space. One such optimization that has been exploited in this paper is the shift-inclusive computation reordering to minimize the width of every two's complement adder to further reduce the implementation cost and the critical path delay of the filter. Experiment results show that the proposed algorithm can contribute up to 19.30% reductions in logic complexity and up to 61.03% reduction in critical path delay over other minimization methods.

Design and Optimization of Reversible BCD Adder/Subtractor Circuit for Quantum and Nanotechnology Based Systems

Abstract: Reversible logic circuits have found emerging attention in nanotechnology, quantum computing and low power CMOS designs. In this paper we present a modular synthesis method to realize a reversible Binary Coded Decimal (BCD) adder/subtractor circuit. We use genetic algorithms and don't care concept to design and optimize all parts of a BCD adder circuit in terms of number of garbage inputs/outputs and the quantum cost. We have also developed and used genetic algorithm-based synthesis software to design and optimize proper circuits for a reversible BCD adder/subtractor such as full adder, reversible 9's complement generator and reversible multiplexer. The results show improvement in the quantum cost, the number of garbage inputs and outputs.

A Power-Delay Efficient Hybrid Carry-Lookahead/Carry-Select Based Redundant Binary to Two's Complement Converter

Abstract: This paper presents an efficient reverse converter for transforming the redundant binary (RB) representation into two's complement form. The hierarchical expansion of the carry equation for the reverse conversion algorithm creates a regular multilevel structure, from which a high-speed hybrid carry-lookahead/carry-select (CLA/CSL) architecture is proposed to fully exploit the redundancy of RB encoding for VLSI efficient implementation. The optimally designed CSL sections interleaved evenly in the mixed-radix CLA network to boost the performance of the reverse converter well above those designed based on a homogeneous type of carry propagation adder. The logical effort characterization captures the effect of circuit's fan-in, fan-out and transistor sizing on performance, and the evaluation shows that our proposed architecture leads to the fastest design. A 64-bit transistor-level circuit implementation of our proposed reverse converter and that of its most competitive contender were simulated to validate the logical effort delay model. The pre- and post-layout HSPICE simulation results reveal that our new converter expends at least two times less energy (power-delay product) than the competitor circuit and is capable of completing a 64-bit conversion in 829 ps and dissipates merely 5.84 mW at a data rate of 1 GHz and a supply voltage of 1.8 V in TSMC 0.18-mum CMOS technology.

QCA based multiplexing of 16 arithmetic & logical subsystems-A paradigm for nano computing

Abstract: In this work, we make use of a new computing paradigm quantum cellular automata (QCA) to describe the design and layout of arithmetic and logical function generator (ALFG). ALFG is made up of several blocks whose outputs are multiplexed for an intended functionality. The design of ALFG was made using the basic elements of technology such as inverter and majority voter. The layout and simulation results are presented using QCADesigner tool. A total of 16 arithmetic and logical operations can be performed on a pair of 4bit vectors. The ALFG presented, offers functions beyond a normal ALU such as shift, parity, XOR, rotate and multiplication along with basic operations. The total area consumed by ALFG is 11.37 mum2 with aid of 9 clocks to give the final output from the generator. The building blocks of ALFG can be added into a 4bit processor in order to make it feasible for additional applications.

A Unifying Approach for Weighted and Diminished-1 Modulo $2^n+1$ Addition

Abstract: In this paper, it is shown that every architecture proposed for modulo 2n+1 addition of operands that follow the diminished-1 representation can also be used in the design of modulo 2n+1 adders for operands that follow the weighted representation. This is achieved by the addition of a constant-time operator composed of a simplified carry-save adder stage. The experimental results indicate that many architectures already proposed for the diminished-1 case, lead to very efficient adders for weighted operands, under this unifying approach.

Physical Demonstration of Polymorphic Self-Checking Circuits

Abstract: Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized in a self-checking polymorphic adder. This paper presents an experimental evaluation of this novel implementation.