Showing papers on "Adder published in 2010"

Bio-Inspired Imprecise Computational Blocks for Efficient VLSI Implementation of Soft-Computing Applications

Abstract: The conventional digital hardware computational blocks with different structures are designed to compute the precise results of the assigned calculations. The main contribution of our proposed Bio-inspired Imprecise Computational blocks (BICs) is that they are designed to provide an applicable estimation of the result instead of its precise value at a lower cost. These novel structures are more efficient in terms of area, speed, and power consumption with respect to their precise rivals. Complete descriptions of sample BIC adder and multiplier structures as well as their error behaviors and synthesis results are introduced in this paper. It is then shown that these BIC structures can be exploited to efficiently implement a three-layer face recognition neural network and the hardware defuzzification block of a fuzzy processor.

Design of Low-Power High-Speed Truncation-Error-Tolerant Adder and Its Application in Digital Signal Processing

Abstract: In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.

Enhanced low-power high-speed adder for error-tolerant application

Abstract: The tradeoff between power consumption and speed performance has become a major design consideration when devices approach the sub-100 nm regime. It is especially critical when dealing with large data set, whereby the system is degraded in terms of power and speed. If the application can accept some errors, i.e. the application is Error — tolerant (ET), a large reduction in power and an increased in speed can be simultaneously achieved. In this paper, we shall present a novel low-power and high-speed Error-Tolerant Adder Type IV design called ETAIV. The proposed ETAIV is an enhancement of our earlier design, ETAII [1] in terms of speed and accuracy.

A Reduced Complexity Wallace Multiplier Reduction

Abstract: Wallace high-speed multipliers use full adders and half adders in their reduction phase. Half adders do not reduce the number of partial product bits. Therefore, minimizing the number of half adders used in a multiplier reduction will reduce the complexity. A modification to the Wallace reduction is presented that ensures that the delay is the same as for the conventional Wallace reduction. The modified reduction method greatly reduces the number of half adders; producing implementations with 80 percent fewer half adders than standard Wallace multipliers, with a very slight increase in the number of full adders.

ULPFA: A New Efficient Design of a Power-Aware Full Adder

Abstract: In this paper, we first propose a new structure of a hybrid full adder, namely, the branch-based logic and pass-transistor (BBL-PT) cell, which we implemented by combining branch-based logic and pass-transistor logic. Evolution of the proposed cell from its original version to an ultralow-power (ULP) cell is described. Quantitative comparisons of the optimized version, namely, the ULP full adder (ULPFA), are carried out versus the BBL-PT full adder and its counterparts in two well-known and commonly used logic styles, i.e., conventional static CMOS logic and complementary pass logic (CPL), in a 0.13-μm PD SOI CMOS with a supply voltage of 1.2 V, demonstrating power delay product (PDP) and static power performance that are more than four times better than CPL design. This could lead to tremendous benefit for multiplier application. The implementation of an 8-bit ripple carry adder based on the ULPFA is finally described, and comparisons between adders based on full adders from the prior art and our ULPFA version demonstrate that our development outperforms the static CMOS and the CPL full adders, particularly in terms of power consumption and PDP by at least a factor of two.

Binary Adders on Quantum-Dot Cellular Automata

Abstract: This article describes the design of adder units on quantum-dot cellular automata (QCA) nanotechnology, which promises very dense circuits and high operating frequencies, using a single homogeneous layer of the basic cells. We construct pipelined structures without the earlier noise problems, avoided by careful clocking organization, and the modular layouts are verified with the QCADesigner coherence vector simulation. Our designs occupy only a fraction of area compared to the previous noise rejecting design, while having also superior performance, and it is shown that the wiring overhead of the arithmetic circuits on QCA grows with square-law dependence on the operand word length. Power analysis at the fundamental Landauer's limit shows, that the operating frequencies will indeed be bound by the energy dissipated in information erasure: under irreversible operation, the clock rates of the adder units on molecular QCA are only tens of gigahertz, while the switching speed of the technology is in the terahertz regime.

A highly area-efficient controller for capacitive touch screen panel systems

Abstract: In this paper, a highly area-efficient controller for capacitive touch screen panels (TSPs) is proposed. The proposed controller uses a 10-bit successive approximation register analog-to-digital converter (SAR ADC) with an adder to compensate for the capacitance variation in the TSP and for the offset voltage variation in the charge amplifier of the sensing circuit. By using the proposed compensation method, the area of the controller can be reduced by 90.3% of the area of the conventional controllers. The measurement results showed that the signal-to-noise ratio (SNR) of the controller increases from 12.5 to 21.3 dB after compensation. Also, its spatial jitter decreases from ±1.5 to ±0.46 mm, which is 7% of the sensor pitch of 8 mm.

Improved Design of High-Performance Parallel Decimal Multipliers

Abstract: The new generation of high-performance decimal floating-point units (DFUs) is demanding efficient implementations of parallel decimal multipliers. In this paper, we describe the architectures of two parallel decimal multipliers. The parallel generation of partial products is performed using signed-digit radix-10 or radix-5 recodings of the multiplier and a simplified set of multiplicand multiples. The reduction of partial products is implemented in a tree structure based on a decimal multioperand carry-save addition algorithm that uses unconventional (non BCD) decimal-coded number systems. We further detail these techniques and present the new improvements to reduce the latency of the previous designs, which include: optimized digit recoders for the generation of 2n-tuples (and 5-tuples), decimal carry-save adders (CSAs) combining different decimal-coded operands, and carry-free adders implemented by special designed bit counters. Moreover, we detail a design methodology that combines all these techniques to obtain efficient reduction trees with different area and delay trade-offs for any number of partial products generated. Evaluation results for 16-digit operands show that the proposed architectures have interesting area-delay figures compared to conventional Booth radix-4 and radix--8 parallel binary multipliers and outperform the figures of previous alternatives for decimal multiplication.

A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator

Abstract: Conventional continuous-time (CT) delta-sigma (??) analog-to-digital converters (ADCs) consume large amount of power in operational amplifiers of a loop-filter. We propose a new loop-filter with single-opamp resonator, ringing-relaxation filter and passive resistor adder to lower power consumption. These three techniques are essential for designing high-order delta sigma modulators with low oversampling ratio. Because the new resonator reduces the number of opamps, the resistor adder displaces a conventional active adder and the ringing-relaxation filter alleviates the burden on the first opamp by reducing its gain bandwidth, FOM is greatly improved. To demonstrate the concept, 300 MHz, fifth-order low-pass, 3-bit CT?? ADC of single feedback with feedforward architecture was implemented in a 1.1 V, 110 nm 1P6M CMOS process. An SNR of 68.2 dB and an SNDR of 62.5 dB were measured in a 10 MHz bandwidth and FOM was 0.24 pJ/conv.

A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm

Abstract: In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into CSA, the overall performance was elevated. The proposed CSA tree uses 1's-complement-based radix-2 modified Booth's algorithm (MBA) and has the modified array for the sign extension in order to increase the bit density of the operands. The CSA propagates the carries to the least significant bits of the partial products and generates the least significant bits in advance to decrease the number of the input bits of the final adder. Also, the proposed MAC accumulates the intermediate results in the type of sum and carry bits instead of the output of the final adder, which made it possible to optimize the pipeline scheme to improve the performance. The proposed architecture was synthesized with 250, 180 and 130 ?m, and 90 nm standard CMOS library. Based on the theoretical and experimental estimation, we analyzed the results such as the amount of hardware resources, delay, and pipelining scheme. We used Sakurai's alpha power law for the delay modeling. The proposed MAC showed the superior properties to the standard design in many ways and performance twice as much as the previous research in the similar clock frequency. We expect that the proposed MAC can be adapted to various fields requiring high performance such as the signal processing areas.

True Energy-Performance Analysis of the MTJ-Based Logic-in-Memory Architecture (1-Bit Full Adder)

Abstract: The use of spin-transfer torque (STT) devices for memory design has been a subject of research since the discovery of the STT on MgO-based magnetic tunnel junctions (MTJs). Recently, MTJ-based computing architectures such as logic-in-memory have been proposed and claim superior energy-delay performance over static CMOS. In this paper, we conduct exhaustive energy-performance analysis of an STT-MTJ-based logic-in-memory (LIM-MTJ) 1-bit full adder and compare it with its corresponding CMOS counterpart. Our results show that the LIM-MTJ circuit has no advantage in energy-performance over its equivalent CMOS designs. We also show that the MTJ-based logic circuit requiring frequent MTJ switching during the operation is hardly power efficient.

Improved Carry Select Adder with Reduced Area and Low Power Consumption

Abstract: Power dissipation is one of the most important design objectives in integrated circuits, after speed. As adders are the most widely used components in such circuits, design of efficient adder is of much concern for researchers. This paper presents performance analysis of different Fast Adders. The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. We present a modified carry select adder designed in different stages. Results obtained from modified carry select adders are better in area and power consumption . Categories and Subject Descriptors VHDL, Behavioural modeling, General Terms Carry select adder, multiple stage adder Keywords Adder, Carry select Adder, carry skip adder, VHDL Simulation 1. INTRODUCTION compact Addition usually impacts widely the overall performance of digital systems and a crucial arithmetic function. In electronic applications adders are most widely used. Applications where these are used are multipliers, DSP to execute various algorithms like FFT, FIR and IIR. Wherever concept of multiplication comes adders come in to the picture. As we know millions of instructions per second are performed in microprocessors. So, speed of operation is the most important constraint to be considered while designing multipliers. Due to device portability miniaturization of device should be high and power consumption should be low. Devices like Mobile, Laptops etc. require more battery backup. So, a VLSI designer has to optimize these three parameters in a design. These constraints are very difficult to achieve so depending on demand or application some compromise between constraints has to be made. Ripple carry adders exhibits the most compact design but the slowest in speed. Whereas carry lookahead is the fastest one but consumes more area [2]. Carry select adders act as a compromise between the two adders. In 2002, a new concept of hybrid adders is presented to speed up addition process by Wang et al. that gives hybrid carry look-ahead/carry select adders design [7]. In 2008, low power multipliers based on new hybrid full adders is presented in [8]. In 2008, Hasan Krad et al provided the performance analysis for a 32-Bit Multiplier with a Carry look-ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL and showed that CLA multiplier is almost double in speed as compared to RCA multiplier [9]. The rest of the paper is organized as follows. In section 2, a brief about ripple carry adder, carry skip and variable carry skip is given. In the same section carry select adder is introduced along with partitioning methodology. Also a new architecture with clock sharing is introduced. Section 3 provides the results obtained. Section 4 concludes the paper

Low Power Reversible Parallel Binary Adder/Subtractor

Abstract: In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.

High Speed Capacitor-Inverter Based Carbon Nanotube Full Adder

Abstract: Carbon Nanotube filed-effect transistor (CNFET) is one of the promising alternatives to the MOS transistors. The geometry-dependent threshold voltage is one of the CNFET characteristics, which is used in the proposed Full Adder cell. In this paper, we present a high speed Full Adder cell using CNFETs based on majority-not (Minority) function. Presented design uses eight transistors and eight capacitors. Simulation results show significant improvement in terms of delay and power-delay product in comparison to contemporary CNFET Adder Cells. Simulations were carried out using HSPICE based on CNFET model with 0.6 V VDD.

Principles and construction of MSD adder in ternary optical computer

Abstract: The two remarkable features of ternary values and a massive unit with thousands bits of parallel computation will make the ternary optical computer (TOC) with modified signed-digit (MSD) adder more powerful and efficient than ever before for numerical calculations. Based on the decrease-radix design presented previously, a TOC can satisfy either a user requiring huge capacity for data calculations or one with a moderate amount of data, if it is equipped with a prepared adder. Furthermore, with the application of pipelined operations and the proposed data editing technique, the efficiency of the prepared adder can be greatly improved, so that each calculated result can be obtained almost within one clock cycle. It is hopeful that by employing a MSD adder, users will be able to enter a new dimension with the creation of a new multiplier, new divider, as well as new matrix operator in a TOC in the near future.

A 1.2-ns16×16-Bit Binary Multiplier Using High Speed Compressors

Abstract: � Abstract—For higher order multiplications, a huge number of adders or compressors are to be used to perform the partial product addition. We have reduced the number of adders by introducing special kind of adders that are capable to add five/six/seven bits per decade. These adders are called compressors. Binary counter property has been merged with the compressor property to develop high order compressors. Uses of these compressors permit the reduction of the vertical critical paths. A 16×16 bit multiplier has been developed using these compressors. These compressors make the multipliers faster as compared to the conventional design that have been used 4-2 compressors and 3-2 compressors. Keywords—Binary multiplier, Compressors, Counter, Column adder, Low power.

Energy-Efficient Design Methodologies: High-Performance VLSI Adders

Abstract: Energy-efficient design requires exploration of available algorithms, recurrence structures, energy and wire tradeoffs, circuit design techniques, circuit sizing and system constraints. In this paper, methodology for energy-efficient design applied to 64-bit adders implemented with static CMOS, dynamic CMOS and CMOS compound domino logic families, is presented. We also examined 65 nm, 45 nm, 32 nm, and 22 nm technology nodes to explore the applicability of the results in deep submicron technologies. By applying energy-delay tradeoffs on various levels, we developed adder topology yielding up to 20% performance improvement and 4.5× energy reduction over existing designs.

A digital phase-locked loop clock system

Abstract: A clock system includes a digital phase/frequency detector (DPFD), a buffer, a digitallycontrolled oscillator (DCa) including a sigma- delta modulator (SDM), an adder, a first frequency divider. The DPFD may have a first input for a reference input clock, a second input for a feedback signal, the DPFD generating an output representing a difference between the reference input clock and the feedback signal. The buffer may be coupled to the DPFD for accumulating the difference signal over time. The sigma-delta modulator (SDM) may have a control input coupled to the buffer. The adder may have inputs coupled to the (SDM) and a source of an integer control word.

Memristor-based arithmetic

Abstract: This paper describes strategies for performing arithmetic operations in memristor-based structures An overview of both analog and digital approaches offered in the literature for addition and multiplication will be described Memristor-based designs of an adder and a multiplier are presented

Voltage Scalable High-Speed Robust Hybrid Arithmetic Units Using Adaptive Clocking

Abstract: In this paper, we explore various arithmetic units for possible use in high-speed, high-yield ALUs operated at scaled supply voltage with adaptive clock stretching. We demonstrate that careful logic optimization of the existing arithmetic units (to create hybrid units) indeed make them further amenable to supply voltage scaling. Such hybrid units result from mixing right amount of fast arithmetic into the slower ones. Simulations on different hybrid adder and multipliers in BPTM 70 nm technology show 18%-50% improvements in power compared to standard adders with only 2%-8% increase in die-area at iso-yield. These optimized datapath units can be used to construct voltage scalable robust ALUs that can operate at high clock frequency with minimal performance degradation due to occasional clock stretching.

A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS

Abstract: Computationally intensive DSP/media processing applications require specialized hardware accelerators to enable higher energy-efficiency on microprocessor platforms. On-die reconfigurable arrays enable flexible accelerators with dynamic on-the-fly programmability while amortizing die area and time-to-market costs across a wide range of workloads. An ultra-low-voltage fine-grained reconfigurable fabric consisting of a hybrid configurable logic block (CLB) array with process/voltage/temperature (PVT) variation-tolerant register file (Fig. 18.2.1), targeted for on-die acceleration of DSP/media algorithms on power-constrained mobile microprocessors, is fabricated in 32nm high-k/metal-gate CMOS [1]. The CLB combines self-decoded look-up tables (LUTs) for random logic with reconfigurable arithmetic building blocks, hybrid 3∶2 compressors with integrated partial product generation, configurable adder/multiplier carry propagation and optimized CLB input/output multiplexers to achieve peak energy-efficiency of 2.6TOPS/W measured at 340mV, 50°C. The register file includes programmable stacked shared keepers and interruptible operation of both write memory cells and set-dominant latches (SDLs), improving V cc -min by 300mV across PVT variations with a wide dynamic operating range of 320mV–1.2V, enabling simultaneous dynamic supply/frequency optimization across target workloads and power budgets. These features also achieve: (i) nominal CLB performance of 2.4GHz, 5.3mW measured at 1.0V, (ii) robust CLB functionality measured at 260mV, 27MHz (sub-threshold) consuming 12µW, (iii) scalable register file performance up to 8.2GHz, 125mW measured at 1.2V, 50°C with low-voltage near-threshold operation at 320mV, 252MHz consuming 430µW, (iv) 4-tap FIR filter, radix-2 FFT butterfly and 16b string-match algorithms with peak throughput of 2.1GSamples/s, 2.4GSamples/s and 100Gbps respectively, and (v) application-dependent dual-supply power savings up to 34%.

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance

Abstract: In this paper, we proposed a new adder design called variable-latency adder (VL-adder). This technique allows the adder to work at a lower supply voltage than that required by a conventional adder while maintaining the same throughput. The VL-adder design can be further modified to overcome the effects of negative bias temperature instability (NBTI) on circuit delay. By applying VL-adder concept to a 64-bit carry-select adder design, more than 40% energy saving is obtained when a similar throughput is maintained.

Circuits, systems, and methods for managing automatic gain control in quadrature signal paths of a receiver

Abstract: A system provides closed-loop gain control in a WCDMA mode and open loop control in an EDGE/GSM mode. Gain control is distributed across analog devices and a digital scaler in a wireless receiver. In the WCDMA mode, a loop filter generates an error signal that is forwarded to analog and digital control paths. The analog control path includes a first adder, a programmable hysteresis element, and a lookup table. The analog control signal is responsive to thresholds, which when used in conjunction with a previous gain value determine a new gain value. The digital control path includes a second adder, a programmable delay element, and a converter. A control word is responsive to a difference of the error signal, a calibration value, and the analog control signal. Blocker detection is provided in the WCDMA mode of operation. A controller sets system parameters using a state machine.

Optimized reversible BCD adder using new reversible logic gates

Abstract: Reversible logic has received great attention in the recent years due to their ability to reduce the power dissipation which is the main requirement in low power digital design. It has wide applications advanced computing, low power CMOS design, Optical information processing, DNA computing, bio information, quantum computation and nanotechnology. This paper presents an optimized reversible BCD adder using a new reversible gate. A comparative result is presented which shows that the proposed design is more optimized in terms of number of gates, number of garbage outputs and quantum cost than the existing designs.

A Low-Cost Very Large Scale Integration Architecture for Multistandard Inverse Transform

Abstract: In this brief, a low-cost very large scale integration (VLSI) architecture is designed for multistandard inverse transform. The proposed architecture is used in multistandard decoder of MPEG-2, MPEG-4 ASP, H.264/AVC and VC-1. Two circuit share strategies, factor share (FS) and adder share (AS), are applied to the inverse transform architecture for saving its circuit resource. It is shown that the proposed multistandard inverse transform architecture can support the real-time decoding of 1920 × 1080@60 Hz high-definition video at the cost of low circuit resource.

Minimal Logic Depth adder tree optimization for Multiple Constant Multiplication

Abstract: Research on optimization of fixed coefficient FIR filters modeled as Multiple Constant Multiplication (MCM) has been ongoing for two decades. An analysis of Minimal Signed Digit (MSD) reveals that potential good solutions are omitted by Common Subexpression Elimination (CSE) algorithms as they are hidden in the MSD representations. Some CSE algorithms ensure that all coefficients are implemented at minimal Logic Depth (LD) which is advantageous from power saving perspective. Imposing this requirement on a graph dependant (GD) algorithm reduces the search space as well as the runtime. It also eliminates the long critical path of GD algorithm. This paper presents a minimal logic depth GD algorithm which requires no lookup table. Simulation results show that it has lower number of adders than CSE algorithms while having the minimal logic depth. For all filters tested, it consumes less switching power than the latest LD constrained GD methods based on the Glitch Path Count and Glitch Path Score metrics.

Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder

Abstract: Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 parity preserving reversible logic gate, IG. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. It is shown that a fault tolerant reversible full adder circuit can be realized using only two IGs. The proposed fault tolerant full adder (FTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

A low-voltage and energy-efficient full adder cell based on carbon nanotube technology

Abstract: Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT (Carbon Nanotube) based transistors. In this paper, a high-speed and energy-efficient CNFET (Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed for nanotechnology. This design is simulated in various supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Significant improvement is achieved in terms of speed and PDP (Power-Delay-Product) in comparison with other classical and state-of-the-art CMOS and CNFET-based designs, existing in the literature. The proposed Full Adder can also drive large load capacitance and works properly in low supply voltages.

An Efficient Delay Model for MOS Current-Mode Logic Automated Design and Optimization

Abstract: MOS current-mode logic (MCML) is a low-noise alternative to CMOS logic. The lack of MCML automation tools, however, has deterred designers from applying MCML to complex digital functions. This paper presents an efficient MCML optimization program that can be used to properly size MCML gates. The delay model accuracy is adjusted by fitting measured gate delays by means of technology-dependent parameters. For an N number of logic gates, the proposed mathematical program has reduced the number of variables to N+1, in comparison to 7N+1 in the most recent work on this topic. The program has been implemented to efficiently optimize a 4-bit ripple carry adder and an 8-bit decoder in 0.18-μm CMOS technology.