Showing papers on "Adder published in 2012"

Accuracy-configurable adder for approximate arithmetic designs

Abstract: Approximation can increase performance or reduce power consumption with a simplified or inaccurate circuit in application contexts where strict requirements are relaxed. For applications related to human senses, approximate arithmetic can be used to generate sufficient results rather than absolutely accurate results. Approximate design exploits a tradeoff of accuracy in computation versus performance and power. However, required accuracy varies according to applications, and 100% accurate results are still required in some situations. In this paper, we propose an accuracy-configurable approximate (ACA) adder for which the accuracy of results is configurable during runtime. Because of its configurability, the ACA adder can adaptively operate in both approximate (inaccurate) mode and accurate mode. The proposed adder can achieve significant throughput improvement and total power reduction over conventional adder designs. It can be used in accuracy-configurable applications, and improves the achievable tradeoff between performance/power and quality. The ACA adder achieves approximately 30% power reduction versus the conventional pipelined adder at the relaxed accuracy requirement.

Low-Power and Area-Efficient Carry Select Adder

Abstract: Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.

Low Complexity Design of Ripple Carry and Brent–Kung Adders in QCA

Abstract: The design of adders on quantum dot cellular automata (QCA) has been of recent interest. While few designs exist, investigations on reduction of QCA primitives (majority gates and inverters) for various adders are limited. In this paper, we present a number of new results on majority logic. We use these results to present efficient QCA designs for the ripple carry adder (RCA) and various prefix adders. We derive bounds on the number of majority gates for -bit RCA and -bit Brent-Kung, Kogge-Stone, Ladner-Fischer, and Han-Carlson adders. We further show that the Brent-Kung adder has lower delay than the best existing adder designs as well as other prefix adders. In addition, signal integrity and robustness studies show that the proposed Brent-Kung adder is fairly well-suited to changes in time-related parameters as well as temperature. Detailed simulations using QCADesigner are presented.

CMOS-based carbon nanotube pass-transistor logic integrated circuits.

Abstract: Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.

High performance reliable variable latency carry select addition

Abstract: Speculative adders have attracted strong interest for reducing critical path delays to sub-logarithmic delays by exploiting the trade-offs between reliability and performance. Speculative adders also find use in the design of reliable variable latency adders, which combine speculation with error correction to achieve high performance for low area overhead over traditional adders. This paper describes speculative carry select addition (SCSA), a novel function speculation technique for the design of low error-rate speculative adders and low overhead, high performance, reliable variable latency adders. We develop an analytical model for the error rate of SCSA to facilitate both design exploration and convergence. We show that for an error rate of 0.01% (0.25%), SCSA-based speculative addition is 10% faster than the DesignWare adder with up to 43% (56%) area reduction. Further, on average, variable latency addition using SCSA-based speculative adders is 10% faster than the DesignWare adder with area requirements of -19% to 16% (-17% to 29%) for unsigned random (signed Gaussian) inputs.

Area, Delay And Power Comparison Of Adder Topologies

Abstract: Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. This paper presents the pertinent choice for selecting the adder topology with the tradeoff between delay, power consumption and area. The adder topology used in this work are ripple carry adder, carry lookahead adder, carry skip adder, carry select adder, carry increment adder, carry save adder and carry bypass adder. The module functionality and performance issues like area, power dissipation and propagation delay are analyzed at 0.12 µm 6metal layer CMOS technology using microwind tool.

Modeling and synthesis of quality-energy optimal approximate adders

Abstract: Recent interest in approximate computation is driven by its potential to achieve large energy savings. This paper formally demonstrates an optimal way to reduce energy via voltage over-scaling at the cost of errors due to timing starvation in addition. We identify a fundamental trade-off between error frequency and error magnitude in a timing-starved adder. We introduce a formal model to prove that for signal processing applications using a quadratic signal-to-noise ratio error measure, reducing bit-wise error frequency is sub-optimal. Instead, energy-optimal approximate addition requires limiting maximum error magnitude. Intriguingly, due to possible error patterns, this is achieved by reducing carry chains significantly below what is allowed by the timing budget for a large fraction of sum bits, using an aligned, fixed internal-carry structure for higher significance bits. We further demonstrate that remaining approximation error is reduced by realization of conditional bounding (CB) logic for lower significance bits. A key contribution is the formalization of an approximate CB logic synthesis problem that produces a rich space of Pareto-optimal adders with a range of quality-energy tradeoffs. We show how CB logic can be customized to result in over-and under-estimating approximate adders, and how a dithering adder that mixes them produces zero-centered error distributions, and, in accumulation, a reduced-variance error. We demonstrate synthesized approximate adders with energy up to 60% smaller than that of a conventional timing-starved adder, where a 30% reduction is due to the superior synthesis of inexact CB logic. When used in a larger system implementing an image-processing algorithm, energy savings of 40% are possible.

A Novel Design for Quantum-dot Cellular Automata Cells and Full Adders

Abstract: Quantum dot Cellular Automata (QCA) is a novel and potentially attractive technology for implementing computing architectures at the nanoscale. The basic Boolean primitive in QCA is the majority gate. In this paper we present a novel design for QCA cells and another possible and unconventional scheme for majority gates. By applying these items, the hardware requirements for a QCA design can be reduced and circuits can be simpler in level and gate counts. As an example, a 1-bit QCA adder is constructed by applying our new scheme and is compared to the other existing implementation. Beside, some Boolean functions are expressed as examples and it has been shown, how our reduction method by using new proposed item, decreases gate counts and levels in comparison to the other previous methods.

An efficient quantum-dot cellular automata full-adder

Abstract: The most important mathematical operation is addition. Other operations such as subtraction, multiplication and division are usually implemented by adders. An efficient adder can be of great assistance in designing arithmetic circuits. QCA is a promising technology which seems to be a good candidate for the next generation of digital systems. So, an efficient QCA full-adder will facilitate creating QCA computational and arithmetic systems. In this paper, two high performances QCA full-adders are presented. They have a very dense structure and constructed using new kinds of five-input majority gates. One of the proposed designs has a robust structure. In this design the presented design rules for constructing a robust QCA circuit have been considered. In contrast to the previous designs constructed using a five-input majority gate, in the proposed QCA full-adders the outputs come out from the same side of the circuit. Also, the input and output signals are not surrounded by the other cells and can easily be accessed. The proposed robust QCA full-adder dominates all the previous robust designs in terms of area, delay and complexity. Using this design, ripple carry adders with different word sizes (that is, 4, 8 and 16) are constructed. In this paper, QCA designer, a common QCA layout design and verification tool is employed to verify and simulate the proposed five-input majority gates and QCA full-adders. Key words: Quantum-dot cellular automata, full-adder, five-input majority gate, robustness, ripple carry adder.

An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term

Abstract:  Abstract—In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic simplification and sharing partial circuit, we only need one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation. Through the multiplexer, we can select the correct output result according to the logic state of carry-in signal. In this way, the transistor count in a 32-bit carry select adder can be greatly reduced from 1947 to 960. Moreover, the power consumption can be reduced from 1.26mw to 0.37mw as well as power delay product reduced from 2.14mw*ns to 1.28mw*ns.

Designing novel reversible BCD adder and parallel adder/subtraction using new reversible logic gates

Abstract: Reversible logic has received much attention in recent years when calculation with minimum energy consumption is considered. Especially, interest is sparked in reversible logic by its applications in some technologies, such as quantum computing, low-power CMOS design, optical information processing and nanotechnology. This article proposes two new reversible logic gates, ZRQ and NC. The first gate ZRQ not only implements all Boolean functions but also can be used to design optimised adder/subtraction architectures. One of the prominent functionalities of the proposed ZRQ gate is that it can work by itself as a reversible full adder/subtraction unit. The second gate NC can complete overflow detection logic of Binary Coded Decimal (BCD) adder. This article proposes two approaches to design novel reversible BCD adder using new reversible gates. A comparative result which is presented shows that the proposed designs are more optimised in terms of number of gates, garbage outputs, quantum costs and unit delays...

Ultrafast All-Optical Half Adder Using Quantum-Dot Semiconductor Optical Amplifier-Based Mach-Zehnder Interferometer

Abstract: Interferometric devices have drawn a great interest in all-optical signal processing for their high-speed photonic activity. Quantum-dot semiconductor optical amplifier (QD-SOA)-based gate has added a new momentum in this field to perform all-optical logic and algebraic operations. In this paper, a new and alternative scheme for all-optical half adder using two QD-SOA-based Mach-Zehnder interferometers is theoretically investigated and demonstrated. The proposed scheme is driven by the pair of input data streams for one switch between which the Boolean xor function is to be executed to produce sum-bit. Then the output of the first switch and one of the input data are utilized to drive the second switch to produce carry-bit. The impact of the peak data power as well as of the QD-SOAs current density, small signal gain, and QD-SOAs length on the ER and Q-factor of the switching outcome are explored and assessed by means of numerical simulation. The operation of the system is demonstrated with 160 Gbit/s.

FPGA accelerator for floating-point matrix multiplication

Abstract: This study treats architecture and implementation of a field-programmable gate array (FPGA) accelerator for doubleprecision floating-point matrix multiplication. The architecture is oriented towards minimising resource utilisation and maximising clock frequency. It employs the block matrix multiplication algorithm which returns the result blocks to the host processor as soon as they are computed. This avoids output buffering and simplifies placement and routing on the chip. The authors show that such architecture is especially well suited for full-duplex communication links between the accelerator and the host processor. The architecture requires the result blocks to be accumulated by the host processor; however, the authors show that typically more than 99% of all arithmetic operations are performed by the accelerator. The implementation focuses on efficient use of embedded FPGA resources, in order to allow for a large number of processing elements (PEs). Each PE uses eight Virtex-6 DSP blocks. Both adders and multipliers are deeply pipelined and use several FPGA-specific techniques to achieve small area size and high clock frequency. Finally, the authors quantify the performance of accelerator implemented in Xilinx Virtex-6 FPGA, with 252 PEs running at 403 MHz (achieving 203.1 Giga FLOPS (GFLOPS)), by comparing it to double-precision matrix multiplication function from MKL, ACML, GotoBLAS and ATLAS libraries executing on Intel Core2Quad and AMD Phenom X4 microprocessors running at 2.8 GHz. The accelerator performs 4.5 times faster than the fastest processor/library pair.

A digital neuromorphic VLSI architecture with memristor crossbar synaptic array for machine learning

Abstract: This paper presents a reconfigurable digital neuromorphic VLSI architecture for large scale spiking neural networks. We leverage the memristor nanodevice to build an N×N crossbar array to store synaptic weights with significantly reduced area cost. Our design integrates N digital leaky integrate-and-fire (LIF) neurons and the respective on-line learning circuits for a spike timing-dependent learning rule. The proposed analog-to-digital conversion scheme accumulates pre-synaptic weights of a neuron efficiently and reduces silicon area by using only one shared adder for processing LIF operations of N neurons. The proposed architecture is shown to be both area and power efficient. With 256 neurons and 64K synapses, the power dissipation and the area of our design are evaluated as 9.46-mW and 0.66-mm2, respectively, in a 90-nm CMOS technology.

Performing Four Basic Arithmetic Operations With Spiking Neural P Systems

Abstract: Recently, Gutierrez-Naranjo and Leporati considered performing basic arithmetic operations on a new class of bio-inspired computing devices-spiking neural P systems (for short, SN P systems). However, the binary encoding mechanism used in their research looks like the encoding approach in electronic circuits, instead of the style of spiking neurons (in usual SN P systems, information is encoded as the time interval between spikes). In this work, four SN P systems are constructed as adder, subtracter, multiplier, and divider, respectively. In these systems, a number is inputted to the system as the interval of time elapsed between two spikes received by input neuron, the result of a computation is the time between the moments when the output neuron spikes.

On Modulo 2^n+1 Adder Design

Abstract: Two architectures for modulo 2n+1 adders are introduced in this paper. The first one is built around a sparse carry computation unit that computes only some of the carries of the modulo 2n+1 addition. This sparse approach is enabled by the introduction of the inverted circular idempotency property of the parallel-prefix carry operator and its regularity and area efficiency are further enhanced by the introduction of a new prefix operator. The resulting diminished-1 adders can be implemented in smaller area and consume less power compared to all earlier proposals, while maintaining a high operation speed. The second architecture unifies the design of modulo 2n ± 1 adders. It is shown that modulo 2n+1 adders can be easily derived by straightforward modifications of modulo 2n-1 adders with minor hardware overhead.

Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits

Abstract: We present an adaptive technique for compensating manufacturing and environmental variability in subthreshold circuits using “canary flip-flop (FF),” which can predict timing errors. A 32-bit Kogge-Stone adder whose performance was controlled by body-biasing was fabricated in a 65-nm CMOS process. Measurement results show that the adaptive control can compensate process, supply voltage, and temperature variations and improve the energy efficiency of subthreshold circuits by up to 46% compared to worst-case design and operation with guardbanding. We also discuss how to determine design parameters, such as the inserted location and the buffer delay of the canary FF, supposing two approaches: configuration in the design phase and post-silicon tuning.

Mach-zehnder interferometer based design of all optical reversible binary adder

Abstract: In recent years reversible logic has emerged as a promising computing model for applications in dissipation less optical computing, low power CMOS, quantum computing, etc. In reversible circuits there exist a one-to-one mapping between the inputs and the outputs resulting in no loss of information. Researchers have implemented reversible logic gates in optical computing domain as it can provide high speed and low energy requirement along with easy fabrication at the chip level [1]. The all optical implementation of reversible gates are based on semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI) due to its significant advantages such as high speed, low power, fast switching time and ease in fabrication. In this work we present the all optical implementation of an n bit reversible ripple carry adder for the first time in literature. The all optical reversible adder design is based on two new optical reversible gates referred as optical reversible gate I (ORG-I) and optical reversible gate II (ORG-II) and the existing all optical Feynman gate. The two new reversible gates ORG-I and ORGI-I are proposed as they can implement a reversible adder with reduced optical cost which is the measure of number of MZIs switches and the propagation delay, and with zero overhead in terms of number of ancilla inputs and the garbage outputs. The proposed all optical reversible adder design based on the ORG-I and ORG-II reversible gates are compared and shown to be better than the other existing designs of reversible adder proposed in non-optical domain in terms of number of MZIs, delay, number of ancilla inputs and the garbage outputs. The proposed all optical reversible ripple carry adder will be a key component of an all optical reversible ALU that can be applied in a wide variety of optical signal processing applications.

Design and analysis of a high-performance CNFET-based Full Adder

Abstract: This article presents a high-speed and high-performance Carbon Nanotube Field Effect Transistor (CNFET) based Full Adder cell for low-voltage applications. The proposed Full Adder cell is composed of two separate modules with identical hardware configurations which generate the Sum and C out signals in a parallel manner. The great advantage of the proposed structure is its very short critical path which is composed of only two carbon nanotube pass-transistors. This design also takes advantage of the unique properties of metal oxide semiconductor field effect transistor-like CNFETs such as the feasibility of adjusting the threshold voltage of a CNFET by adjusting the diameter of its nanotubes to correct the voltage levels as well as to achieve a high performance. Comprehensive experiments are performed in various situations to evaluate the performance of the proposed design. Simulations are carried out using Synopsys HSPICE with 32-nm Complementary Metal Oxide Semiconductor (CMOS) and 32-nm CNFET technolog...

New Decomposition Theorems on Majority Logic for Low-Delay Adder Designs in Quantum Dot Cellular Automata

Abstract: The design of low-delay multibit adders in quantum dot cellular automata is considered in this brief. We present a general approach for delay reduction based on two new theorems called decomposition theorems. We consider the carry-lookahead adder (CLA) and the carry-flow adder (CFA) as specific applications of the theorems. For 16-bit CLA and 16-bit CFA, the decomposition theorems yield reductions in delay for the leading carry of approximately 60% and 25%, respectively, when compared to the best existing designs. In addition, the decomposition theorems lead to designs with low area-delay product. Simulations in QCADesigner are also presented.

A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform

Abstract: In this paper, a scheme for the design of a high-speed pipeline VLSI architecture for the computation of the 2-D discrete wavelet transform (DWT) is proposed. The main focus in the development of the architecture is on providing a high operating frequency and a small number of clock cycles along with an efficient hardware utilization by maximizing the inter-stage and intra-stage computational parallelism for the pipeline. The inter-stage parallelism is enhanced by optimally mapping the computational task of multi decomposition levels to the stages of the pipeline and synchronizing their operations. The intra-stage parallelism is enhanced by dividing the 2-D filtering operation into four subtasks that can be performed independently in parallel and minimizing the delay of the critical path of bit-wise adder networks for performing the filtering operation. To validate the proposed scheme, a circuit is designed, simulated, and implemented in FPGA for the 2-D DWT computation. The results of the implementation show that the circuit is capable of operating with a maximum clock frequency of 134 MHz and processing 1022 frames of size 512 × 512 per second with this operating frequency. It is shown that the performance in terms of the processing speed of the architecture designed based on the proposed scheme is superior to those of the architectures designed using other existing schemes, and it has similar or lower hardware consumption.

Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance

Abstract: This paper presents the design and characterization of 12 full-adder circuits in the IBM 90-nm process. These include three new full-adder circuits using the recently proposed split-path data driven dynamic logic. Based on the logic function realized, the adders were characterized for performance and power consumption when operated under various supply voltages and fan-out loads. The adders were then further deployed in a 32 bit ripple carry adder and 8×4 multiplier to evaluate the impact of sum and carry propagation delays on the performance, power of these systems. Performance characterization of the adder circuits in the presence of process and voltage variations was also performed through Monte Carlo simulations. Besides analyzing and comparing circuit performance, the possible impact of the choice of logic function has also been underlined in this study.

Pipelined adder graph optimization for high speed multiple constant multiplication

Abstract: This paper addresses the direct optimization of pipelined adder graphs (PAGs) for high speed multiple constant multiplication (MCM). The optimization opportunities are described and a definition of the pipelined multiple constant multiplication (PMCM) problem is given. It is shown that the PMCM problem is a generalization of the MCM problem with limited adder depth (AD). A novel algorithm to solve the PMCM problem heuristically, called RPAG, is presented. RPAG outperforms previous methods which are based on pipelining the solutions of conventional MCM algorithms. A flexible cost evaluation is used which enables the optimization for FPGA or ASIC targets on high or low abstraction levels. Results for both technologies are given and compared with the most recent methods. Even for the special case of limited AD it is shown that RPAG often produces better results compared to the prominent Hcub algorithm with minimal total AD constraint.

Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design

Abstract: This paper presents a comparative study of high-speed and low-voltage full adder circuits. Our approach is based on hybrid design full adder circuits combined in a single unit. A high performance adder cell using an XOR-XNOR (3T) design style is discussed. This paper also discusses a high-speed conventional full adder design combined with MOSCAP Majority function circuit in one unit to implement a hybrid full adder circuit. Moreover, it presents low-power Majority-function-based 1-bit full addersthat use MOS capacitors (MOSCAP) in its structure. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits over the conventional CMOS, TG, and hybrid adder circuits in terms of power, delay, power delay product (PDP), and energy delay product (EDP). Postlayout simulation results illustrate the superiority of the newly designed majority adder circuits against the reported conventional adder circuits. The design is implemented on UMC0.18 µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single-ended supply voltage, and simulations are carried out on Spectre S.

New Methodology for the Design of Efficient Binary Addition Circuits in QCA

Abstract: The quantum-dot cellular automata (QCA) approach is an attractive emerging technology suitable for the development of ultradense low-power high-performance digital circuits. Even though several solutions have been proposed recently for binary addition circuits, the design of efficient adders in QCA still poses several challenges since, most often, designers tend to implement strategies and methodologies close to those consolidated for the CMOS logic design. In this paper, we propose a new design method that exploits in original ways the properties of auxiliary propagate and generates signals to reduce the number of majority gates required to implement adders in QCA and/or the addition time. Three new formulations of basic logic equations frequently used in the designs of fast binary adders are proposed. To evaluate the potential advantage of the new strategy, two examples of application of the aforementioned method are discussed in this paper.

Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm

Abstract: Based on fast FIR algorithms (FFAs), this brief proposes new parallel FIR filter architectures, which are beneficial to symmetric convolutions of odd length in terms of the hardware cost. The proposed parallel FIR architectures exploit the inherent nature of symmetric coefficients reducing half the number of multipliers in the subfilter section at the expense of increase in adders in preprocessing and postprocessing blocks. Exchanging multipliers with adders is advantageous because adders weigh less than multipliers in terms of silicon area, and in addition, the overhead from the increase in adders in preprocessing and postprocessing blocks stay fixed, not increasing along with the length of the FIR filter, whereas the number of reduced multipliers increases along with the length of the FIR filter. For example, for a three-parallel 81-tap filter, the proposed structure saves 26 multipliers at the expense of five adders, whereas for a three-parallel 591-tap filter, the proposed structure saves 196 multipliers at the expense of five adders still. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric convolution in odd length from the existing FFA parallel FIR filter, particularly when the length of the filter is large.

Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis

Abstract: Conventional circuit dissipates energy to reload missing information because of overlapped mapping between input and output vectors. Reversibility recovers energy loss and prevents bit error by including Fault Tolerant mechanism. Reversible Computing is gaining the popularity of various fields such as Quantum Computing, DNA Informatics and CMOS Technology etc. In this paper, we have proposed the fault tolerant design of Reversible Full Adder (RFT-FA) with minimum quantum cost. Also we have proposed the cost effective design of Carry Skip Adder (CSA) and Carry Look-Ahead Adder (CLA) circuits by using proposed fault tolerant full adder circuit. The regular structures of n-bit Reversible Fault Tolerant Carry Skip Adder (RFT-CSA) and Carry Look-ahead Adder (RFT-CLA) by composing several theorems. Proposed designs have been populated by merging the minimization of total gates, garbage outputs, quantum cost and critical path delay criterion and comparing with exiting designs.