Showing papers on "Adder published in 2014"
TL;DR: The IMPLY logic gate, a memristor-based logic circuit, is described and a methodology for designing this logic family is proposed, based on a general design flow suitable for all deterministic memristive logic families.
Abstract: Memristors are novel devices, useful as memory at all hierarchies. These devices can also behave as logic circuits. In this paper, the IMPLY logic gate, a memristor-based logic circuit, is described. In this memristive logic family, each memristor is used as an input, output, computational logic element, and latch in different stages of the computing process. The logical state is determined by the resistance of the memristor. This logic family can be integrated within a memristor-based crossbar, commonly used for memory. In this paper, a methodology for designing this logic family is proposed. The design methodology is based on a general design flow, suitable for all deterministic memristive logic families, and includes some additional design constraints to support the IMPLY logic family. An IMPLY 8-bit full adder based on this design methodology is presented as a case study.
526 citations
24 Mar 2014
TL;DR: It is shown that by utilizing an appropriate error recovery, the proposed approximate multiplier achieves similar processing accuracy as traditional exact multipliers but with significant improvements in power and performance.
Abstract: Approximate circuits have been considered for error-tolerant applications that can tolerate some loss of accuracy with improved performance and energy efficiency. Multipliers are key arithmetic circuits in many such applications such as digital signal processing (DSP). In this paper, a novel approximate multiplier with a lower power consumption and a shorter critical path than traditional multipliers is proposed for high-performance DSP applications. This multiplier leverages a newly-designed approximate adder that limits its carry propagation to the nearest neighbors for fast partial product accumulation. Different levels of accuracy can be achieved through a configurable error recovery by using different numbers of most significant bits (MSBs) for error reduction. The approximate multiplier has a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared to the Wallace multiplier, a 16-bit approximate multiplier implemented in a 28nm CMOS process shows a reduction in delay and power of 20% and up to 69%, respectively. It is shown that by utilizing an appropriate error recovery, the proposed approximate multiplier achieves similar processing accuracy as traditional exact multipliers but with significant improvements in power and performance.
225 citations
TL;DR: All the redundant logic operations present in the conventional C SLA are eliminated and a new logic formulation for CSLA is proposed, in which the carry select (CS) operation is scheduled before the calculation of-final-sum, which is different from the conventional approach.
Abstract: In this brief, the logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA are analyzed to study the data dependence and to identify redundant logic operations. We have eliminated all the redundant logic operations present in the conventional CSLA and proposed a new logic formulation for CSLA. In the proposed scheme, the carry select (CS) operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit patterns of two anticipating carry words (corresponding to $c_{\rm in} = 0\ \hbox{and}\ 1$ ) and fixed $c_{\rm in}$ bits are used for logic optimization of CS and generation units. An efficient CSLA design is obtained using optimized logic units. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. Due to the small carry-output delay, the proposed CSLA design is a good candidate for square-root (SQRT) CSLA. A theoretical estimate shows that the proposed SQRT-CSLA involves nearly 35% less area–delay–product (ADP) than the BEC-based SQRT-CSLA, which is best among the existing SQRT-CSLA designs, on average, for different bit-widths. The application-specified integrated circuit (ASIC) synthesis result shows that the BEC-based SQRT-CSLA design involves 48% more ADP and consumes 50% more energy than the proposed SQRT-CSLA, on average, for different bit-widths.
138 citations
TL;DR: In this paper, it is demonstrated that it is possible to synthesize a stochastic flash ADC entirely from Verilog code and a standard digital library, and a prototype IC is fabricated in 90 nm CMOS and implements a 2047-comparator version of the proposed architecture.
Abstract: It is demonstrated in this paper that it is possible to synthesize a stochastic flash ADC entirely from Verilog code and a standard digital library. An analog comparator is introduced that is constructed from two cross-coupled 3-input digital NAND gates, and can be described in Verilog. The synthesized comparators have random, Gaussian offsets that are used as virtual voltage references to make a flash ADC. A piecewise-linear inverse Gaussian CDF function is used to correct the nonlinearity introduced by the Gaussian offset distribution. The prototype IC is fabricated in 90 nm CMOS and implements a 2047-comparator version of the proposed architecture. All components including the comparators, the ones adder, and the peicewise inverse Gaussian function are all implemented in Verilog. Conventional digital synthesis and place-and-route is then used to generate the physical layout, making this the first fully synthesized ADC. SNDR of 35.9 dB (without calibration) is achieved at 210 MSPS from the Verilog synthesized design.
102 citations
TL;DR: A new 8-bit full adder is designed based on the majority gate in the QCA, with the minimum number of cells and area which combines both designs to implement an8-bit adder/subtractor in theQCA, which has the minimum delay and complexity.
102 citations
TL;DR: A novel 5-input majority gate, an important fundamental building block in QCA circuits, is designed in a symmetric form and demonstrated to perform equally well or in many cases better than previous circuits.
Abstract: By the inevitable scaling down of the feature size of the MOS transistors which are deeper in nanoranges, the CMOS technology has encountered many critical challenges and problems such as very high leakage currents, reduced gate control, high power density, increased circuit noise sensitivity and very high lithography costs. Quantum-dot cellular automata (QCA) owing to its high device density, extremely low power consumption and very high switching speed could be a feasible competitive alternative. In this paper, a novel 5-input majority gate, an important fundamental building block in QCA circuits, is designed in a symmetric form. In addition to the majority gate, a SR latch, a SR gate and an efficient one bit QCA full adder are implemented employing the new 5-input majority gate. In order to verify the functionality of the proposed designs, QCADesigner tool is used. The results demonstrate that the proposed SR latch and full adder perform equally well or in many cases better than previous circuits.
91 citations
TL;DR: In this paper, the optical switching phenomena has been studied and its efficient application to construct the fulladder/subtractor (A/S) has been projected and the mathematical description of proposed device and thereafter compilation using MATLAB.
86 citations
TL;DR: The design, construction, and demonstration of a nanoelectronic finite-state machine, fabricated using a design-oriented approach enabled by a deterministic, bottom–up assembly process that does not require individual nanowire registration, which suggests that proposed general-purpose nanocomputers can be realized in the near future.
Abstract: Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine. The system was fabricated using a design-oriented approach enabled by a deterministic, bottom-up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoelectronic finite-state machine through modular design using a multitile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoelectronic finite-state machine integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive intertile and intratile communication that exhibits rigorous input/output matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a finite-state machine or computer. The programmable multitile circuit was also reprogrammed to a functionally distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our unique design-oriented deterministic methodology to yield more extensive multitile systems suggest that proposed general-purpose nanocomputers can be realized in the near future.
77 citations
TL;DR: A new high-performance Ternary Full Adder (TFA) based on Carbon Nanotube Field-Effect Transistor (CNTFET) technology is presented and shows approximately more than 53 % improvement in Power-Delay Product (PDP) compared to its counterparts.
Abstract: The Full Adder is one of the most important and basic units of mathematic circuits that is the basic structure of many complex systems. Moreover, serial and serial-parallel mathematic processes can be carried out faster and more operative error-detection and error-correction codes can be employed in ternary logic implementations. In this work, we presented a new high-performance Ternary Full Adder (TFA) based on Carbon Nanotube Field-Effect Transistor (CNTFET) technology. The proposed design is well-matched with the Carbon Nanotube Field-effect Transistor knowledge and ternary logic value. The presented structure reduces the delay of the Ternary Full Adder and has high driving capability. The proposed Ternary Full Adder is simulated at varying supply voltages and temperatures using different frequencies by the Synopsys HSPICE circuit simulator. Simulation results determine improvement in terms of delay and Power-Delay Product (PDP) in comparison with the state-of-the-art designs. Simulations show that the proposed Ternary Full Adder cell shows approximately more than 53 % improvement in PDP compared to its counterparts.
76 citations
TL;DR: Full Swing Gate Diffusion Input (FS-GDI) methodology is presented and results show 2x area reduction, 5x improvement in dynamic energy dissipation and 4x decrease in leakage, with a slight degradation in performance when compared to the CMOS CLA.
71 citations
TL;DR: Two new symmetric designs for Low-Power full adder cells featuring GDI (Gate-Diffusion Input) structure and hybrid CMOS logic style are presented, which successfully operate at low voltages with tremendous signal integrity and driving capability.
TL;DR: A new adder is proposed that outperforms all state-of-the-art competitors and achieves the best area-delay tradeoff and is obtained by using an overall area similar to the cheaper designs known in literature.
Abstract: As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit, even though the design of logic modules in QCA is not always straightforward. In this brief, we propose a new adder that outperforms all state-of-the-art competitors and achieves the best area-delay tradeoff. The above advantages are obtained by using an overall area similar to the cheaper designs known in literature. The 64-bit version of the novel adder spans over 18.72 μ2 of active area and shows a delay of only nine clock cycles, that is just 36 clock phases.
05 Jan 2014
TL;DR: The proposed binary tree based design methodology for NxN reversible quantum multiplier performs the addition of partial products in parallel using the reversible ripple quantum adders with no garbage output and ancilla bit, thereby minimizing the number of anCilla and garbage bits used in the design.
Abstract: Reversible logic has emerged as a promising computing paradigm having applications in quantum computing, optical computing, dissipation less computing and low power computing etc. In reversible logic there exists a one to one mapping between the input and output vectors. Reversible circuits require constant ancilla inputs for reconfiguration of gate functions and garbage outputs that help in keeping reversibility. Quantum circuits of many qubits are extremely difficult to realize thus reduction in the number of ancilla inputs and the garbage outputs is the primary goal of optimization. In existing literature researchers have proposed several designs of reversible quantum multipliers based on reversible full adders and reversible half adders. The use of reversible full adders and the half adders for the addition of partial products increases the overhead in terms of number of ancilla inputs and number of garbage outputs. This paper presents a binary tree based design methodology for a NxN reversible quantum multiplier. The proposed binary tree based design methodology for NxN reversible quantum multiplier performs the addition of partial products in parallel using the reversible ripple quantum adders with no garbage output and ancilla bit, thereby minimizing the number of ancilla and garbage bits used in the design. The proposed design methodology shows the improvement of 17.86% to 60.34% in terms of ancilla inputs; and 21.43% to 52.17% in terms of garbage outputs compared to all the existing reversible quantum multiplier designs.
01 Dec 2014
TL;DR: An optimized memristor-based full adder design by material implication logic is presented, which needs 27 memristors and less area in comparison with typical CMOS-based 8-bit full adders.
Abstract: Recently memristor-based applications and circuits are receiving an increased attention. Furthermore, memristors are also applied in logic circuit design. Material implication logic is one of the main areas with memristors. In this paper an optimized memristor-based full adder design by material implication logic is presented. This design needs 27 memristors and less area in comparison with typical CMOS-based 8-bit full adders. Also the presented full adder needs only 184 computational steps which enhance former full adder design speed by 20 percent.
TL;DR: In this article, a photodiode-based logic device employing scalable heterojunctions of carbon nanotubes and silicon whose output currents can be manipulated by both optical and electrical inputs is developed.
Abstract: A photodiode-based logic device employing scalable heterojunctions of carbon nanotubes and silicon whose output currents can be manipulated by both optical and electrical inputs is developed Bidirectional phototransistors and novel clock-triggerable logic elements, such as a mixed optoelectronic AND gate, a 2-Bit optoelectronic ADDER/OR gate and a 4-Bit optoelectronic D/A converter, are also demonstrated
TL;DR: The resource minimization problem in the scheduling of adder-tree operations for the MCM block is identified, and a mixed integer programming (MIP) based algorithm for more efficient MCM-based implementation of FIR filters is presented.
Abstract: Multiple constant multiplication (MCM) scheme is widely used for implementing transposed direct-form FIR filters. While the research focus of MCM has been on more effective common subexpression elimination, the optimization of adder-trees, which sum up the computed sub-expressions for each coefficient, is largely omitted. In this paper, we have identified the resource minimization problem in the scheduling of adder-tree operations for the MCM block, and presented a mixed integer programming (MIP) based algorithm for more efficient MCM-based implementation of FIR filters. Experimental result shows that up to 15% reduction of area and 11.6% reduction of power (with an average of 8.46% and 5.96% respectively) can be achieved on the top of already optimized adder/subtractor network of the MCM block.
Patent•
10 Jan 2014TL;DR: In this paper, the authors provided a drive control method for a motor including multiple sets of coils and drive circuits in an electric power steering system, which includes an electrical angle estimator, an α-axis voltage component adder and a β-axis current component adders that add together voltage vectors of a first coil and a second coil expressed in a two-phase fixed coordinate system, and an induced voltage computing unit that computes an voltage based on an added voltage vector and an added current vector.
Abstract: There is provided a drive control method for a motor including multiple sets of coils and drive circuits in an electric power steering system. In order to reduce computational load when sensorless control is executed, an electrical angle estimator includes an α-axis voltage component adder and a β-axis voltage component adder that add together voltage vectors of a first coil and a second coil expressed in a two-phase fixed coordinate system, an α-axis current component adder and a β-axis current component adder that add together current vectors of the first coil and the second coil expressed in a two-phase fixed coordinate system, and an induced voltage computing unit that computes an induced voltage based on an added voltage vector and an added current vector.
TL;DR: The proposed full adder design uses only two QCA1 gates and maximizes the circuit density and focuses on a layout of the circuit which is minimal in using QCA cells.
Abstract: Quantum-dot cellular automata (QCA) technique is one of the emerging and promising nanotechnologies. It has considerable advantages versus CMOS technology in various aspects such as extremely low power dissipation, high operating frequency and small size. In this paper, designing of a one-bit full adder is investigated using a QCA implementation of Toffoli and Fredkin gates. Then, a full adder design with reversible QCA1 gates is proposed regarding to overhead and power savings. Our proposed full adder design is more preferable when considering both circuit area and speed. The proposed design uses only two QCA1 gates and maximizes the circuit density and focuses on a layout of the circuit which is minimal in using QCA cells.
TL;DR: In this article, the authors propose an efficient algorithm to synthesize prefix graph structures that yield adders with the best performance-area trade-off, which can handle more complex constraints such as maximum node fanout or wire-length that impact the performance/area of a design.
Abstract: This paper proposes an efficient algorithm to synthesize prefix graph structures that yield adders with the best performance-area trade-off. For designing a parallel prefix adder of a given bit-width, our approach generates prefix graph structures to optimize an objective function such as size of prefix graph subject to constraints like bit-wise output logic level. Besides having the best performance-area trade-off our approach, unlike existing techniques, can (i) handle more complex constraints such as maximum node fanout or wire-length that impact the performance/area of a design and (ii) generate several feasible solutions that minimize the objective function. Generating several optimal solutions provides the option to choose adder designs that mitigate constraints such as wire congestion or power consumption that are difficult to model as constraints during logic synthesis. Experimental results demonstrate that our approach improves performance by 3% and area by 9% over even a 64-bit full custom designed adder implemented in an industrial high-performance design.
TL;DR: By a combination of graphene oxide and DNA, a universal platform was developed for integration of multiple logic gates to implement both half adder and half subtractor functions.
01 Sep 2014
TL;DR: Two types of reversible ALU designs are proposed and verified using Altera Quartus II software and the simulation results show that the proposed reversible ALu design 2 outperforms the proposedversible ALU design 1 and conventional ALUDesign.
Abstract: In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU)In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software In the proposed designs, eight arithmetic and four logical operations are performed In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2 Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design
TL;DR: A method to integrate an (in principle) unlimited number of molecular logic gates to construct complex circuits is presented and this process is demonstrated on a four-bit full adder.
Abstract: A method to integrate an (in principle) unlimited number of molecular logic gates to construct complex circuits is presented. Logic circuits, such as half- or full-adders, can be reinterpreted by using the functional completeness of the implication function (IMP) and the trivial FALSE operation. The molecular gate IMP is represented by a fluorescent boronic acid sugar probe. An external wiring algorithm translates the fluorescent output from one gate into a chemical input for the next gate on microtiter plates. This process is demonstrated on a four-bit full adder.
TL;DR: Carbon nanotube field-effect transistors are used to form the novel circuits, which are entirely suitable for practical applications and consumes 2.33 µW less power than the one implemented by the previous adder cells.
Abstract: New ternary adders, which are fundamental components of ternary addition, are presented in this paper They are on the basis of a logic style which mostly generates binary signals Therefore, static power dissipation reaches its minimum extent Extensive different analyses are carried out to examine how efficient the new designs are For instance, the ternary ripple adder constructed by the proposed ternary half and full adders consumes 233 µW less power than the one implemented by the previous adder cells It is almost twice faster as well Due to their unique superior characteristics for ternary circuitry, carbon nanotube field-effect transistors are used to form the novel circuits, which are entirely suitable for practical applications
TL;DR: An architecture and implementation method of modified signed-digit (MSD) optical adder from the point of applicability and shows, the MSD adder not only has a reasonable and correct design, but also has high throughput rate, can work efficiently and steadily.
Abstract: How to fully apply the characteristics and advantages of light in numerical computation is an important issue that attracts many scholars. Though much research has been done in this field, how to design and realize specific applications or devices is still an issue to be solved. Based on this, we present an architecture and implementation method of modified signed-digit (MSD) optical adder from the point of applicability. In the implementation, we fully consider the different procedures of the MSD addition which including optical logical operation, results decoding, special storage area design, data feedback, control of light path, etc. Meanwhile, we also introduce pipeline mechanism which guarantees that the addition operation is an automatic and continuous process. This is a carry free adder design method which guarantees the addition has high data throughput. It is very suitable to fulfill the large-scale numerical computation. The experiment shows, the MSD adder not only has a reasonable and correct design, but also has high throughput rate, can work efficiently and steadily.
TL;DR: An area-efficient self-repairing adder that can repair multiple faults and identify the particular faulty full adder and can handle up to four faults effectively, with an 80% probability of error recovery compared to triple modular redundancy, which can handle only a single fault at a time.
TL;DR: A significant advancement in organism-based computing, providing a solid basis for hybrid computers of the future is demonstrated, with combinational logic circuits at least as accurate as previous logic approximations using spatial growth of P. polycephalum and up to 30 times as fast at computing the logical output.
Abstract: Physarum polycephalum is a large single amoeba cell, which in its plasmodial phase, forages and connects nearby food sources with protoplasmic tubes. The organism forages for food by growing these tubes towards detected foodstuff, this foraging behaviour is governed by simple rules of photoavoidance and chemotaxis. The electrical activity of the tubes oscillates, creating a peristaltic like action within the tubes, forcing cytoplasm along the lumen; the frequency of this oscillation controls the speed and direction of growth. External stimuli such as light and food cause changes in the oscillation frequency. We demonstrate that using these stimuli as logical inputs we can approximate logic gates using these tubes and derive combinational logic circuits by cascading the gates, with software analysis providing the output of each gate and determining the input of the following gate. Basic gates OR, AND and NOT were correct 90%, 77.8% and 91.7% of the time respectively. Derived logic circuits XOR, half adder and full adder were 70.8%, 65% and 58.8% accurate respectively. Accuracy of the combinational logic decreases as the number of gates is increased, however they are at least as accurate as previous logic approximations using spatial growth of P. polycephalum and up to 30 times as fast at computing the logical output. The results shown here demonstrate a significant advancement in organism-based computing, providing a solid basis for hybrid computers of the future.
TL;DR: The half adder has also been realized and has achieved an accurate performance and the proposed schemes omit the requirement for an optical delay line or costly O-E-O conversions which makes the system flexible.
Abstract: All-optical signal processing plays an important role in the development of ultrahigh speed optical networks. All-optical logic schemes, such as OR, AND, NOT, and XOR gates, are projected using semiconductor optical amplifiers. Further, to verify the results of proposed logical gates, the half adder has also been realized and has achieved an accurate performance. The proposed schemes omit the requirement for an optical delay line or costly O-E-O conversions which makes the system flexible.
06 Mar 2014
TL;DR: In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay performance and these adders' delay, power and area are investigated and compared finally.
Abstract: In Very Large Scale Integration (VLSI) designs, Parallel prefix adders (PPA) have the better delay performance This paper investigates four types of PPA's (Kogge Stone Adder (KSA), Spanning Tree Adder (STA), Brent Kung Adder (BKA) and Sparse Kogge Stone Adder (SKA)) Additionally Ripple Carry Adder (RCA), Carry Lookahead Adder (CLA) and Carry Skip Adder (CSA) are also investigated These adders are implemented in verilog Hardware Description Language (HDL) using Xilinx Integrated Software Environment (ISE) 132 Design Suite These designs are implemented in Xilinx Virtex 5 Field Programmable Gate Arrays (FPGA) and delays are measured using Agilent 1692A logic analyzer and all these adder's delay, power and area are investigated and compared finally
01 Jul 2014
TL;DR: It is shown that perpendicular Nanomagnetic Logic (pNML) is particularly suitable to realize threshold logic gate (TLG)-based circuits and the theory and results substantiate the feasibility and the benefits of the combination of threshold logic with pNML.
Abstract: In this paper, we show that perpendicular Nanomagnetic Logic (pNML) is particularly suitable to realize threshold logic gate (TLG)-based circuits. Exemplarily, a 1-bit full adder circuit using a novel 5-input majority gate based on TLGs is experimentally demonstrated. The theory of pNML and its extension by TLGs is introduced, illustrating the great benefit of pNML. Majority gates based on coupling field superposition enable weighting each input by its geometry and distance to the output. Only 5 magnets, combined in two logic gates with a footprint of 1.95 μm 2 and powered by a perpendicular clocking field, are required for operation. MFM and magneto-optical measurements demonstrate the functionality of the fabricated structure. Experimental results substantiate the feasibility and the benefits of the combination of threshold logic with pNML.
13 Oct 2014
TL;DR: An improved version of the reversible gates, namely the Feynman Gate and the Toffoli Gate, were implemented in QCA technology using QCADesigner to realize a reversible QCA full adder.
Abstract: Both quantum-dot cellular automata (QCA) and reversible logic are emerging technologies that are promising alternatives to overcoming the scaling and heat dissipation issues, respectively, in the current CMOS designs. Here, the fundamentals of QCA and reversible logic are studied; the feasibility of incorporating reversible logic in QCA designs is also demonstrated. Based on two existing designs, an improved version of the reversible gates, namely the Feynman Gate and the Toffoli Gate, were implemented in QCA technology using QCADesigner. The proposed design of the QCA-based Feynman Gate is faster by ½ cycle as compared to the existing design; while the proposed Toffoli Gate has the same latency as the existing design but it is readily to be cascaded into a more complex design. A 4-bit ripple carry adder in QCA is then designed using the proposed Feynman and Toffoli gates to realize a reversible QCA full adder. This 4-bit QCA adder with reversible logic consists of 2030 QCA cells, has a latency of 7 clock cycles and 8 garbage outputs.