Showing papers on "Adder published in 2015"

A low latency generic accuracy configurable adder

Abstract: High performance approximate adders typically comprise of multiple smaller sub-adders, carry prediction units and error correction units In this paper, we present a low-latency generic accuracy configurable adder to support variable approximation modes It provides a higher number of potential configurations compared to state-of-the-art, thus enabling a high degree of design flexibility and trade-off between performance and output quality An error correction unit is integrated to provide accurate results for cases where high accuracy is required Furthermore, an associated scheme for error probability estimation allows convenient comparison of different approximate adder configurations without requiring the need to numerically simulate the adder Our experimental results validate the developed error model and also the lower latency of our generic accuracy configurable adder over state-of-the-art approximate adders For functional verification and prototyping, we have used a Xilinx Virtex-6 FPGA Our adder model and synthesizable RTL are made open-source

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

Abstract: In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 $\mu $ W) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 $\mu $ W and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79- $\mu $ W (53.36- $\mu $ W) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.

Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover

Abstract: We use a coplanar QCA crossover architecture in the design of QCA full adders that leads to reduction of QCA cell count and area consumption without any latency penalty. This crossover uses non-adjacent clock zones for the two crossing wires. We further investigate the impact of these gains on carry flow QCA adders. These designs have been realized with QCADesigner, evaluated, and tested for correctness. For better performance comparison with previous relevant works, we use a QCA-specific cost function, as well as the conventional evaluation method. We show 23% cell count and 48% area improvements over the best previous QCA full adder design. Similar results for 4-, 8-, 16-, 32-, and 64-bit adders are 29% (22%), 24% (51%), 19% (54%), 13% (69%), and 9% (49%) cell count reduction (less area consumption), respectively.

A Comparative Review and Evaluation of Approximate Adders

Abstract: As an important arithmetic module, the adder plays a key role in determining the speed and power consumption of a digital signal processing (DSP) system. The demands of high speed and power efficiency as well as the fault tolerance nature of some applications have promoted the development of approximate adders. This paper reviews current approximate adder designs and provides a comparative evaluation in terms of both error and circuit characteristics. Simulation results show that the equal segmentation adder (ESA) is the most hardware-efficient design, but it has the lowest accuracy in terms of error rate (ER) and mean relative error distance (MRED). The error-tolerant adder type II (ETAII), the speculative carry select adder (SCSA) and the accuracy-configurable approximate adder (ACAA) are equally accurate (provided that the same parameters are used), however ETATII incurs the lowest power-delay-product (PDP) among them. The almost correct adder (ACA) is the most power consuming scheme with a moderate accuracy. The lower-part-OR adder (LOA) is the slowest, but it is highly efficient in power dissipation.

A Complementary Resistive Switch-Based Crossbar Array Adder

Abstract: Redox-based resistive switching devices (ReRAM) are an emerging class of nonvolatile storage elements suited for nanoscale memory applications. In terms of logic operations, ReRAM devices were suggested to be used as programmable interconnects, large-scale look-up tables or for sequential logic operations. However, without additional selector devices these approaches are not suited for use in large scale nanocrossbar memory arrays, which is the preferred architecture for ReRAM devices due to the minimum area consumption. To overcome this issue for the sequential logic approach, we recently introduced a novel concept, which is suited for passive crossbar arrays using complementary resistive switches (CRSs). CRS cells offer two high resistive storage states, and thus, parasitic “sneak” currents are efficiently avoided. However, until now the CRS-based logic-in-memory approach was only shown to be able to perform basic Boolean logic operations using a single CRS cell. In this paper, we introduce two multi-bit adder schemes using the CRS-based logic-in-memory approach. We proof the concepts by means of SPICE simulations using a dynamical memristive device model of a ReRAM cell. Finally, we show the advantages of our novel adder concept in terms of step count and number of devices in comparison to a recently published adder approach, which applies the conventional ReRAM-based sequential logic concept introduced by Borghetti

Efficient in-memory computing architecture based on crossbar arrays

Abstract: To solve the "big data" problems that are hindered by the Von Neumann bottleneck and semiconductor device scaling limitation, a new efficient in-memory computing architecture based on crossbar array is developed. The corresponding basic operation principles and design rules are proposed and verified using emerging nonvolatile devices such as very low-power resistive random access memory (RRAM). To prove the computing architecture, we demonstrate a parallel 1-bit full adder (FA) both by experiment and simulation. A 4-bit multiplier (Mult.) is further obtained by a programed 2-bit Mult. and 2-bit FA.

Fast boolean logic mapped on memristor crossbar

Abstract: As the CMOS technology is gradually scaling down to inherent physical device limits, significant challenges emerge related to scalability, leakage, reliability, etc. Alternative technologies are under research for next-generation VLSI circuits. Memristor is one of the promising candidates due to its scalability, practically zero leakage, non-volatility, etc. This paper proposes a novel design methodology for logic circuits targeting memristor crossbars. This methodology allows the optimization of the design of logic function, and their automatic mapping on the memristor crossbar. More important, this methodology supports the execution of Boolean logic functions within constant number of steps independent of its functionality. To illustrate the potential of the proposed methodology, multi-bit adders and multipliers are explored; their incurred delay, area and energy costs are analyzed. The comparison of our approach with state-of-the-art Boolean logic circuits for memristor crossbar architecture shows significant improvement in both delay (4 to 500 x) and energy consumption (1.22 to 3.71 x). The area overhead may decrease (down to 44%) or increase (up to 17%) depending on the circuit's functionality and logic optimization level.

An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders

Abstract: Approximate adders have been considered as a potential alternative for error-tolerant applications to trade off some accuracy for gains in other circuit-based metrics, such as power, area and delay. Existing approximate adder designs have shown substantial advantages in improving many of these operational features. However, the error characteristics of the approximate adders still remain an issue that is not very well understood. A simulation-based method requires both programming efforts and a time-consuming execution for evaluating the effect of errors. This method becomes particularly expensive when dealing with various sizes and types of approximate adders. In this paper, a framework based on analytical models is proposed for evaluating the error characteristics of approximate adders. Error features such as the error rate and the mean error distance are obtained using this framework without developing functional models of the approximate adders for time-consuming simulation. As an example, the estimate of peak signal-to-noise ratios (PSNRs) in image processing is considered to show the potential application of the proposed analysis. This analytical framework provides an efficient method to evaluate various designs of approximate adders for meeting different figures of merit in error-tolerant applications.

Transmission gate-based approximate adders for inexact computing

Abstract: Power dissipation has become a significant concern for integrated circuit design in nanometric CMOS technology. To reduce power consumption, approximate implementations of a circuit have been considered as a potential solution for applications in which strict exactness is not required. In approximate computing, power reduction is achieved through the relaxation of the often demanding requirement of accuracy. In this paper, new approximate adders are proposed for low-power imprecise applications by using logic reduction at the gate level as an approach to relaxing numerical accuracy. Transmission gates are utilized in the designs of two approximate full adders with reduced complexity. A further positive feature of the proposed designs is the reduction of the critical path delay. The approximate adders show advantages in terms of power dissipation over accurate and recently proposed approximate adders. An image processing application is presented using the proposed approximate adders to evaluate the efficiency in power and delay at application level.

Adiabatic quantum-flux-parametron cell library adopting minimalist design

Abstract: We herein build an adiabatic quantum-flux-parametron (AQFP) cell library adopting minimalist design and a symmetric layout. In the proposed minimalist design, every logic cell is designed by arraying four types of building block cells: buffer, NOT, constant, and branch cells. Therefore, minimalist design enables us to effectively build and customize an AQFP cell library. The symmetric layout reduces unwanted parasitic magnetic coupling and ensures a large mutual inductance in an output transformer, which enables very long wiring between logic cells. We design and fabricate several logic circuits using the minimal AQFP cell library so as to test logic cells in the library. Moreover, we experimentally investigate the maximum wiring length between logic cells. Finally, we present an experimental demonstration of an 8-bit carry look-ahead adder designed using the minimal AQFP cell library and demonstrate that the proposed cell library is sufficiently robust to realize large-scale digital circuits.

A learnable parallel processing architecture towards unity of memory and computing.

Abstract: Developing energy-efficient parallel information processing systems beyond von Neumann architecture is a long-standing goal of modern information technologies. The widely used von Neumann computer architecture separates memory and computing units, which leads to energy-hungry data movement when computers work. In order to meet the need of efficient information processing for the data-driven applications such as big data and Internet of Things, an energy-efficient processing architecture beyond von Neumann is critical for the information society. Here we show a non-von Neumann architecture built of resistive switching (RS) devices named “iMemComp”, where memory and logic are unified with single-type devices. Leveraging nonvolatile nature and structural parallelism of crossbar RS arrays, we have equipped “iMemComp” with capabilities of computing in parallel and learning user-defined logic functions for large-scale information processing tasks. Such architecture eliminates the energy-hungry data movement in von Neumann computers. Compared with contemporary silicon technology, adder circuits based on “iMemComp” can improve the speed by 76.8% and the power dissipation by 60.3%, together with a 700 times aggressive reduction in the circuit area.

A new approximate adder with low relative error and correct sign calculation

Abstract: Conventional precise adders need long delay and large power consumption to obtain accurate results. However, in recognition of the error tolerance of some applications such as multimedia processing and machine learning, a few recent works proposed approximate adders that generate inaccurate results occasionally to reduce the delay and power consumption. However, existing approximate adders rarely control the relative error and the potential sign error of the calculation results. In this paper, we propose a novel approximate adder that exploits the generate signals for carry speculation. Furthermore, we introduce a very low-cost error reduction module to effectively control the maximal relative error and a low-overhead sign correction module to fix the sign errors. Compared to the conventional adders, our adder is up to 4.3x faster and saves 47% power for a 32-bit addition. Compared to the existing approximate adders, our adder significantly reduces the maximal relative error and ensures correct sign calculation with comparable area, delay, and power consumption.

High-Throughput Modular Multiplication and Exponentiation Algorithms Using Multibit-Scan–Multibit-Shift Technique

Abstract: Modular exponentiation with a large modulus and exponent is a fundamental operation in many public-key cryptosystems. This operation is usually accomplished by repeating modular multiplications. Montgomery modular multiplication has been widely used to relax the quotient determination. The carry–save adder has been employed to reduce the critical path. This paper presents and evaluates a new and efficient Montgomery modular multiplication architecture based on a new digit serial computation. The proposed architecture relaxes the high-radix partial multiplication to a binary multiplication. It also performs several multiplications of consecutive zero bits in one clock cycle instead of several clock cycles. Moreover, the right-to-left and left-to-right modular exponentiation architectures have been modified to use the proposed modular multiplication architecture as its structural unit. We provide the implementation results on a Xilinx Virtex 5 FPGA demonstrating that the total computation time and throughput rate of the proposed architectures outperform most results so far in the literatures.

Scalability of carbon-nanotube-based thin film transistors for flexible electronic devices manufactured using an all roll-to-roll gravure printing system.

Abstract: To demonstrate that roll-to-roll (R2R) gravure printing is a suitable advanced manufacturing method for flexible thin film transistor (TFT)-based electronic circuits, three different nanomaterial-based inks (silver nanoparticles, BaTiO3 nanoparticles and single-walled carbon nanotubes (SWNTs)) were selected and optimized to enable the realization of fully printed SWNT-based TFTs (SWNT-TFTs) on 150-m-long rolls of 0.25-m-wide poly(ethylene terephthalate) (PET). SWNT-TFTs with 5 different channel lengths, namely, 30, 80, 130, 180, and 230 μm, were fabricated using a printing speed of 8 m/min. These SWNT-TFTs were characterized, and the obtained electrical parameters were related to major mechanical factors such as web tension, registration accuracy, impression roll pressure and printing speed to determine whether these mechanical factors were the sources of the observed device-to-device variations. By utilizing the electrical parameters from the SWNT-TFTs, a Monte Carlo simulation for a 1-bit adder circuit, as a reference, was conducted to demonstrate that functional circuits with reasonable complexity can indeed be manufactured using R2R gravure printing. The simulation results suggest that circuits with complexity, similar to the full adder circuit, can be printed with a 76% circuit yield if threshold voltage (Vth) variations of less than 30% can be maintained.

Memstor, memstance simulations via a versatile 4-port built with new adder and subtractor circuits

Abstract: In this paper, novel voltage-mode (VM) n-channel metal-oxide semiconductor (NMOS) transistor-based analogue adder and subtractor circuits, which, respectively, perform V1+V2 and V1−V2 operations, are presented. The most important feature of the proposed circuits is their extremely simple structures containing only six NMOS transistors. Further, the presented adder and subtractor circuits have high input and low output impedances, resulting in easy cascadability. The post-layout simulations of the proposed circuits have been executed using TSMC 0.25 µm process parameters with ±1.25 V. The area of the suggested circuits is approximately 30 × 13 µm2. Moreover, the topology of a generalised mutator, a versatile 4-port built with an adder and a subtractor, which acts as an ordinary mutator when properly reduced to a 2-port, is offered. A table for simulating lossless inductance, memristor, meminductor, memcapacitor and other elements under suitable termination of the 4-port is given, and three of these element...

High-Performance Low-Power Carry Speculative Addition With Variable Latency

Abstract: Adders are one of the most critical arithmetic circuits in a system and their throughput affects the overall performance of the system. Traditional n-bit adders provide accurate results, but the lower bound of their critical path delay is $\Omega {(\log ~n)}$ . To achieve a critical path delay lower than $\Omega {(\log ~n)}$ , many approximate adders have been proposed. These approximate adders decrease the critical path delay and improve the speed by sacrificing computation accuracy or predicting the computation results. This paper proposes a high-performance low-power carry speculative adder (CSPA). This adder separates the carry generator and sum generator. Only one sum generator is used in a block adder to reduce the critical path delay and area overhead. In addition, to generate 100% accurate results, error detection and recovery circuits are added to the proposed CSPA to construct a variable-latency carry speculative adder (VLCSPA). Instead of recalculating all results, the error detection and recovery circuits find and correct the block adder that generates incorrect partial sum bits, reducing power consumption. The experimental results show that the proposed CSPA achieves a 26.59% delay reduction, a 14.06% area reduction, and a 19.03% power consumption reduction compared to the corresponding values for an existing speculative carry-select adder. The experimental results also show the proposed CSPA can be used to improve image denoising results as well.

Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction

Abstract: With the continuous shrinking of technology node, conventional CMOS logic circuits suffer from high power issues due to both increasing leakage current and long traffic delay. Hybrid non-volatile (NV) logic-in-memory architecture, where emerging NV memories are distributed over a logic-circuit plane, has been widely investigated to overcome these limitations. Magnetic tunnel junction (MTJ) is considered as one of the most promising NV candidates thanks to its non-volatility, fast access speed, infinite endurance and easy 3-D integration with CMOS technology. Recently, several 1-bit NV full-adder (FA) structures using MTJ have been proposed to build low-power high-density arithmetic/logic unit for processors. However, one of their major disadvantages is partial non-volatility since they only use MTJs as one of their operands. For the purpose of extending 1-bit NV-FA to multi-bit structure and realizing full non-volatility, synchronous 8-bit NV-FA architecture is presented in this paper, where all the input signals are stored in MTJs instead of CMOS registers. Three possible structures are proposed with respect to different locations of NV data. By using an industrial CMOS 28 nm design kit and a MTJ compact model, we validated their functionalities and compared their performances in terms of power consumption and area, etc.

A HfO2‐Based Complementary Switching Crossbar Adder

Abstract: Rapid growth of future information technology depends on energy-efficient computation and ultra-high density data storage. Non-volatile redox-based resistive switching memory (ReRAM) devices offer logic-in-memory capabilities and can redefine the von Neumann computer architecture. Especially complementary resistive switches (CRSs) enable the integration of highly dense passive nano-crossbar arrays in 4F2 structure (F is the minimum feature size) without the need of selector devices. To reduce fabrication complexity further, single ReRAM device in complementary switching (CS) mode is a viable option. Here, the implementation of in-memory-adders using Pt|HfO2|Hf|Pt-based CS devices, which are integrated into 1 × n passive crossbar arrays, is reported. First, the feasibility of all CRS-logic functions with these CS devices is shown, which offer high-endurance (109 cycles) under pulse conditions. Afterward, two multi-bit crossbar adders, the Toggle-Cell Adder and the Pre-Calculation Adder, are experimentally demonstrated under pulse conditions realizing addition and subtraction operations. These results prove the functional efficiency of the crossbar adder approach, paving the path for highly advanced ReRAM-based computing-in-memory architectures.

Implementation of Arithmetic Operations With Time-Free Spiking Neural P Systems

Abstract: Spiking neural P systems (SN P systems) are a class of distributed parallel computing devices inspired from the way neurons communicate by means of spikes In most applications of SN P systems, synchronization plays a key role which means the execution of a rule is completed in exactly one time unit (one step) However, such synchronization does not coincide with the biological fact: in biological nervous systems, the execution times of spiking rules cannot be known exactly Therefore, a “realistic” system called time-free SN P systems were proposed, where the precise execution time of rules is removed In this paper, we consider building arithmetical operation systems based on time-free SN P systems Specifically, adder, subtracter, multiplier, and divider are constructed by using time-free SN P systems The obtained systems always produce the same computation result independently from the execution time of the rules

A new quantum-dot cellular automata fault-tolerant full-adder

Abstract: A novel fault-tolerant full-adder for quantum-dot cellular automata is presented. Quantum-dot cellular automata (QCA) is an emerging technology and a possible alternative for semiconductor transistor based technologies. A novel fault-tolerant full-adder is proposed in this paper: This component is suitable for designing fault-tolerant QCA circuits. The redundant version of full-adder is simple in structure and more robust than the standard style for this device. By considering two-dimensional arrays of QCA cells, fault tolerance properties of such block full-adder can be analyzed in terms of misalignment, missing and dislocation cells. In order to verify the functionality of the proposed device, some physical proofs are provided. The results confirm our claims and its usefulness in designing digital circuits.

Variable Latency Speculative Han-Carlson Adder

Abstract: Variable latency adders have been recently proposed in literature. A variable latency adder employs speculation: the exact arithmetic function is replaced with an approximated one that is faster and gives the correct result most of the time, but not always. The approximated adder is augmented with an error detection network that asserts an error signal when speculation fails. Speculative variable latency adders have attracted strong interest thanks to their capability to reduce average delay compared to traditional architectures. This paper proposes a novel variable latency speculative adder based on Han-Carlson parallel-prefix topology that resulted more effective than variable latency Kogge-Stone topology. The paper describes the stages in which variable latency speculative prefix adders can be subdivided and presents a novel error detection network that reduces error probability compared to previous approaches. Several variable latency speculative adders, for various operand lengths, using both Han-Carlson and Kogge-Stone topology, have been synthesized using the UMC 65 nm library. Obtained results show that proposed variable latency Han-Carlson adder outperforms both previously proposed speculative Kogge-Stone architectures and non-speculative adders, when high-speed is required. It is also shown that non-speculative adders remain the best choice when the speed constraint is relaxed.

Design of Arithmetic Circuits in Quantum Dot Cellular Automata Nanotechnology

Abstract: This research monograph focuses on the design of arithmetic circuits in Quantum Dot Cellular Automata (QCA). Using the fact that the 3-input majority gate is a primitive in QCA, the book sets out to discover hitherto unknown properties of majority logic in the context of arithmetic circuit designs. The pursuit for efficient adders in QCA takes two forms. One involves application of the new results in majority logic to existing adders. The second involves development of a custom adder for QCA technology. A QCA adder named as hybrid adder is proposed and it is shown that it outperforms existing multi-bit adders with respect to area and delay. The work is extended to the design of a low-complexity multiplier for signed numbers in QCA. Furthermore the book explores two aspects unique to QCA technology, namely thermal robustness and the role of interconnects. In addition, the book introduces the reader to QCA layout design and simulation using QCADesigner. Features & Benefits: This research-based book: · Introduces the reader to Quantum Dot Cellular Automata, an emerging nanotechnology. · Explores properties of majority logic. · Demonstrates application of the properties to design efficient arithmetic circuits. · Guides the reader towards layout design and simulation in QCADesigner

ERSFQ 8-Bit Parallel Adders as a Process Benchmark

Abstract: We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resistor-free approach to dc biasing of Single Flux Quantum circuits that dissipates orders of magnitude less power than a traditional RSFQ logic while operating and has zero dissipation in inactive mode. The adders were designed for and fabricated with various fabrication processes, including HYPRES's 1.0-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 4-layer 4.5 kA/cm 2 process, HYPRES's 0.25-μm 6-layer 4.5 kA/cm 2 planarized process, and MIT Lincoln Lab's 0.25-μm 4-layer 10 kA/cm 2 process. These circuits serve as a good LSI fabrication process benchmark. We describe design and report on test results of all versions of the adder.

Energy Efficient Approximate Arithmetic for Error Resilient Neuromorphic Computing

Abstract: This brief proposes a novel design scheme for approximate adders and comparators to significantly reduce energy consumption while maintaining a very low error rate. The considerably improved error rate and critical path delay stem from the employed carry prediction technique that leverages the information from less significant input bits in a parallel manner. The proposed designs have been adopted in a VLSI-based neuromorphic character recognition chip with unsupervised learning implemented on chip. The approximation errors of the proposed arithmetic units have been shown to have negligible impact on the training process while archiving good energy efficiency.

A latency optimized biased implementation style weak-indication self-timed full adder

Abstract: This article presents a biased implementation style weak-indication self-timed full adder design that is latency optimized. The proposed full adder is constructed using the delay-insensitive dual-rail code and adheres to 4-phase handshaking. Performance comparisons of the proposed full adder vis-a-vis other strong and weak-indication full adders are done on the basis of a 32-bit self-timed carry-ripple adder architecture, with the full adders and ripple carry adders realized using a 32/28nm CMOS process. The results show that the proposed full adder leads to reduction in latency by 63.3% against the best of the strong-indication full adders whilst reporting decrease in area by 10.6% and featuring comparable power dissipation. On the other hand, when compared with the existing optimized weak-indication full adder, the proposed full adder is found to minimize the latency by 25.1% whilst causing an increase in area by just 1.6%, however, with no associated power penalty.