Adder

About: Adder is a research topic. Over the lifetime, 24942 publications have been published within this topic receiving 200752 citations.

Control circuit for magnetic resolver

Abstract: PURPOSE:To omit an R/D converter and to obtain an inexpensive detector by executing operation by means of an operational amplifier and a phase difference counter to detect a rotational angle. CONSTITUTION:The frequency of a clock from a clock generator 10 is divided by a frequency divider 11, supplied to the coils 9081, 9082 of a resolver 900 as a sine wave through an LPF 11 and then supplied to coils 9091, 9092 as a cosine wave through a phase adjusting means 14. Respective differences between the coils 9081, 9082 and between the coils 9091, 9092 are added by an adder 19 and a phase having the same phase as an excited sine wave is subtracted from the added value by the adder 19 through a phase adjusting means 16 to obtain a sine wave whose phase is shifted from the excited sine wave by the rotational angle of the resolver. The phase difference is measured by a phase difference counter 23 through comparator 21, 22 to use it as a commutation control signal and the period of an output from the comparator 22 is measured by a period counter 24 to calculate a rotating position.

Receiver and receiving method therefor

Abstract: PROBLEM TO BE SOLVED: To improve the receiving performance of a receiver and to make a DC offset non-adjustment at factory shipment. SOLUTION: In this receiver, a DC offset estimation circuit 161 estimates a DC offset quantity from digital data, which adds the DC offset quantity of the preceding receiving signal to a receiving signal and converts it, a conversion circuit 162 converts output data of the circuit 161 with multiplication by a constant, and it is outputted to a conversion value average circuit 163. The circuit 163 averages the DC offset value by a balancing operation, and a DA converter 17 converts output data of the circuit 163 into an analog signal and supplies it to an analog adder 12.

Modular FPGA-based digital ultrasound beamforming

Abstract: The evaluation of ultrasound system is measured by the development in analog and digital electronics. A modular field programmable gate array (FPGA)-based digital ultrasound beamforming is presented. The digital beamforming is implemented in Virtex-5 FPGA. The objective of this work is to develop a modular low-cost PC-based digital ultrasound imaging system that has almost all of its processing steps done on the PC side. The system consists of: two 8 channels block and reconstructed line block. The 8 channel block consist of: memory block to save the samples data after converted to fixed point type, delay block implemented by addressable shift register — the delay process is based on sampled delay focusing (SDF) — and M-code block applied the summation of each RF channel samples. The reconstructed block consists of pipelined adder to apply the summation of the two 8 channels blocks. The power consumption and device utilization was acceptable. Also it is possible to build 16-,32-,64-, and 128-channel beamformer. The hardware architecture of the design provided flexibility for beamforming.

Multithreading to improve cycle width and CPI in superpipelined superscalar processors

Abstract: This paper presents a multithreaded superpipelined superscalar processor design. It is expected to have a sustained rate of 5.4 instructions run per cycle, with 4 threads on chip. Multithreading serves to improve the superscalar CPI by interleaving threads executions. Operator sharing is used instead of out of order execution. It requires less hardware-no reservation stations, collision vectors or renamed registers-and should offer a greater parallelism potential. Arithmetic operators, including adders, shifters, a multiplier and a step divider, have been pipelined to reduce the processor cycle width to a 16 bits adder propagation delay. Separate and equal lengths data paths controlled by a completely RISC instruction set allow efficient in order issue and termination. Floating point operations are emulated with integer ones with data dependent algorithms providing as good latencies as for traditional hardware implementation. A single register file serves for both the integer and the floating point data.