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Amorphous silicon

About: Amorphous silicon is a research topic. Over the lifetime, 26777 publications have been published within this topic receiving 423234 citations.


Papers
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Journal ArticleDOI
TL;DR: The localized state density distribution in the mobility gap of glow-discharge amorphous silicon has been determined from capacitance-voltage characteristics for metal/oxide/amorphous silicon (MOS) structures.
Abstract: The localized state density distribution in the mobility gap of glow‐discharge amorphous silicon has been determined from capacitance‐voltage characteristics for metal/oxide/amorphous silicon (MOS) structures. This new method provides a smooth distribution of localized states throughout the mobility gap. The density of states increases from a minimum of the order of 1016 cm−3 eV−1 near midgap to more than 1018–1019 cm−3 eV−1 within 0.2 eV of the band edges.

119 citations

Patent
20 Oct 2000
TL;DR: An electrode for a lithium cell having an active material thin film absorbing/desorbing lithium such as a microcrystalline silicon thin film or an amorphous silicon thin films provided on a current collector, characterized in that a component of the current collector is diffused into the thin film as discussed by the authors.
Abstract: An electrode for a lithium cell having an active material thin film absorbing/desorbing lithium such as a microcrystalline silicon thin film or an amorphous silicon thin film provided on a current collector, characterized in that a component of the current collector is diffused into the thin film.

119 citations

Journal ArticleDOI
TL;DR: In this article, a diamond turning machine was used to make grooves on (111) p-type single-crystal silicon wafers at room temperature, and the surface of the groove, after machining, was covered by a mixture of metastable, high-pressure silicon phases and amorphous silicon.
Abstract: A single-point diamond turning machine was used to make grooves on (111) p-type single-crystal silicon wafers at room temperature. Scratch tests have been performed with both sharp (Vickers and conical) diamond tools, and a spherical (Rockwell) diamond tool. Our results showed that material removal mechanisms differed between these tools. Pressure-induced metallization of Si allows the ductile regime mechanical micromachining of wafer surfaces. Raman microspectroscopy and electron microscopy were used to determine the machining parameters that do not introduce cracking or other types of damage. The surface of the groove, after machining, was covered by a mixture of metastable, high-pressure silicon phases and amorphous silicon. Further, these phases can be transformed into cubic silicon by annealing. The maximum depth of cut in the ductile regime has been determined for the given scratch test conditions and tools. The developed technique can be used to machine Ge, GaAs and other semiconductors. Applications drawing from this research are many. For example, channels for microfluidic devices can be engraved with a channel cross-section that is determined by the shape of the tool, which allows patterns that cannot be produced using etching. There are no limitations on the channel length or direction, and the channel width can vary from potentially a few nanometres to several micrometres.

119 citations

Journal ArticleDOI
TL;DR: In this paper, molecular-dynamics simulations using the Stillinger-Weber three-body potential are used to synthesize fully dense nanocrystalline silicon with a grain size up to 73 nm by crystallization from the melt.

119 citations

Journal ArticleDOI
TL;DR: In this paper, the use of a silicon oxide interlayer between the active area and the back contact of the cell permits in such cases to improve the electrical properties of the cells, and relative increases of up to 7.5% of fill factor and of 6.8% of conversion efficiency are shown for amorphous silicon cells, together with improved yield and low-illumination performance.
Abstract: The deposition of thin-film silicon solar cells on highly textured substrates results in improved light trapping in the cell. However, the growth of silicon layers on rough substrates can often lead to undesired current drains, degrading performance and reliability of the cells. We show that the use of a silicon oxide interlayer between the active area and the back contact of the cell permits in such cases to improve the electrical properties. Relative increases of up to 7.5% of fill factor and of 6.8% of conversion efficiency are shown for amorphous silicon cells deposited on highly textured substrates, together with improved yield and low-illumination performance.

119 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023118
2022214
2021245
2020422
2019526
2018571