Topic
Amorphous silicon
About: Amorphous silicon is a research topic. Over the lifetime, 26777 publications have been published within this topic receiving 423234 citations.
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TL;DR: In this article, the Schottky barrier was used in thin-film amorphous-silicon solar cells and the current-voltage characteristics were studied in the range from 270 to 370°K and were found to be in agreement with the diffusion theory of metal-semiconductor rectification.
Abstract: Metal–amorphous‐silicon Schottky barriers, similar to those used in thin‐film amorphous‐silicon solar cells, exhibit nearly ideal diode behavior in the dark. The current‐voltage characteristics have been studied in the range from 270 to 370 °K and are found to be in agreement with the diffusion theory of metal‐semiconductor rectification. Barrier heights, which were measured by two different methods, depend on the metal work function, and barriers as high as ∼1.1 eV are obtained with Pt films.
189 citations
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188 citations
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TL;DR: In this paper, a microcrystalline fluorinated p+ silicon alloy has been developed for single and tandem amorphous silicon alloy based solar cells, which has high dark conductivity and low optical loss.
Abstract: We have developed a microcrystalline fluorinated p+ silicon alloy which has high dark conductivity and low optical loss. Incorporation of this material in single and tandem amorphous silicon alloy based solar cells has resulted in increased open circuit voltage and conversion efficiency.
188 citations
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TL;DR: In this article, the electrical properties of metal-oxide-semiconductor capacitors on molecular beam epitaxial GaAs in situ passivated with ultrathin amorphous Si (a-Si) layer and with ex situ deposited HfO2 gate oxide and TaN metal gate were demonstrated.
Abstract: We demonstrate the electrical properties of metal-oxide-semiconductor capacitors on molecular beam epitaxial GaAs in situ passivated with ultrathin amorphous Si (a-Si) layer and with ex situ deposited HfO2 gate oxide and TaN metal gate. Minimum thickness of the Si interface passivation layer of 1.5 nm is needed to prevent the Fermi level pinning and provide good capacitance-voltage characteristics with equivalent oxide thickness of 2.1 nm and leakage current of ⩽1.0mA∕cm2. Transmission electron microscopy analysis showed that the Si layer was oxidized up to 1.4 nm during ex situ processing while the interface between the GaAs and a-Si remained atomically sharp without any sign of interfacial reaction.
187 citations
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TL;DR: In this article, the first few layers of pentacene TFTs are analyzed and the packing and exact arrangement of molecules in these layers determine the current obtained at an applied voltage.
Abstract: Organic semiconductors are attracting considerable research interest due to already commercialized and potential applications in low-cost electronics such as organic light emitting diode (OLED) displays, thin film transistors and related applications (e.g. TFT sensors), RF identification tags (RFID), smart cards electronic paper etc.). In the field of organic semiconductor research, the material pentacene has developed into a benchmark material because high-performance thin film transistor (TFT) devices are easily and robustly obtained from vacuum-deposited thin films of pentacene on a variety of substrates. Pentacene thin films on silicon oxide are a particularly interesting case because, despite their polycrystalline film morphology (i.e. structural imperfections and small grains), the pentacene TFTs outperform single crystalbased pentacene transistors. The key to understanding the electrical performance of pentacene TFTs lies with the first few layers of pentacene. When a TFT device is switched “on”, the current flows predominantly in the first few molecular layers and the packing and exact arrangement of molecules in these layers determine the current obtained at an applied voltage. The knowledge of the precise packing in the first monolayer is, therefore, crucial to understanding the charge transport properties of pentacene TFTs.
187 citations