Showing papers on "Amplifier published in 2003"

A low-power low-noise CMOS amplifier for neural recording applications

Abstract: There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.

Nonlinear Microwave and RF Circuits

Abstract: Preface. Introduction, Fundamental Concepts, and Definitions. Solid-State Device Modeling. Harmonic-Balance analysis. Volterra-Series and Power-Series Analysis. Balanced Circuits. Diode Mixers. Diode Frequency Multipliers. Small-Signal Amplifiers. Power Amplifiers. Active Frequency Multipliers. Active Mixers. Oscillators. Index.

A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification

Abstract: Precision amplifiers dominate the power dissipation in most high-speed pipelined analog-to-digital converters (ADCs). We propose a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages. In the multibit first stage of a 12-bit 75-MSamples/s proof-of-concept prototype, we achieve more than 60% residue amplifier power savings over a conventional implementation. The ADC has been fabricated in a 0.35-/spl mu/m double-poly quadruple-metal CMOS technology and achieves typical differential and integral nonlinearity within 0.5 LSB and 0.9 LSB, respectively. At Nyquist input frequencies, the measured signal-to-noise ratio is 67 dB and the total harmonic distortion is -74 dB. The IC consumes 290 mW at 3 V and occupies 7.9 mm/sup 2/.

A high-speed oscillator-based truly random number source for cryptographic applications on a smart card IC

Abstract: The design of a high-speed IC random number source macro-cell, suitable for integration in a smart card microcontroller, is presented. The oscillator sampling technique is exploited and a jittered oscillator which features an amplified thermal noise source has been designed in order to increase the output throughput and the statistical quality of the generated bit sequences. The oscillator feedback loop acts as an offset compensation for the noise amplifier, thus solving one of the major issues in this kind of circuit. A numerical model for the proposed system has been developed which allows us to carry out an analytical expression for the transition probability between successive bits in the output stream. A prototype chip has been fabricated in a standard digital 0.18 /spl mu/m n-well CMOS process which features a 10 Mbps throughput and fulfills the NIST FIPS and correlation-based tests for randomness. The macro-cell area, excluding pads, is 0.0016 mm/sup 2/ (184 /spl mu/m /spl times/ 86 /spl mu/m) and a 2.3 mW power consumption has been measured.

Electronic device having sound output module

Abstract: the output amplifiers requiring a bias voltage can be activated or deactivated individually, and a bias acceleration circuit for rapidly increasing the magnitude of a bias voltage in time can be provided in or with the bias circuit, whereby even in case of the capacitance of the capacitor included in the bias circuit being increased for improving the power supply rejection ratio (PSRR), the rise in the bias voltage can be increased so that the pop sound which arises when the bias circuit is activated can be still diminished.

10-Gb/s limiting amplifier and laser/modulator driver in 0.18-/spl mu/m CMOS technology

Abstract: A limiting amplifier incorporates active feedback, inductive peaking, and negative Miller capacitance to achieve a voltage gain of 50 dB, a bandwidth of 9.4 GHz, and a sensitivity of 4.6 mV/sub pp/ for a bit-error rate of 10/sup -12/ while consuming 150 mW. A driver employs T-coil peaking and negative impedance conversion to achieve operation at 10 Gb/s while delivering a current of 100 mA to 25-/spl Omega/ lasers or a voltage swing of 2 V/sub pp/ to 50-/spl Omega/ modulators with a power dissipation of 675 mW. Fabricated in 0.18-/spl mu/m CMOS technology, both prototypes operate with a 1.8-V supply.

Distortion in RF power amplifiers

Abstract: Introduction Some Circuit Theory and Terminology Memory Effects in RF Power Amplifiers The Volterra Model Simulating and Measuring Memory Effects Cancellation of Memory Effects Characterization of the Volterra Model Appendix A: Volterra Analysis in More Detail Appendix B: IM3 Equations for Cascaded 2nd-Order Distortion Mechanisms Appendix C: The Truncation Error

The class-E/F family of ZVS switching amplifiers

Abstract: A new family of switching amplifiers, each member having some of the features of both class E and inverse F, is introduced. These class-E/F amplifiers have class-E features such as incorporation of the transistor parasitic capacitance into the circuit, exact truly switching time-domain solutions, and allowance for zero-voltage-switching operation. Additionally, some number of harmonics may be tuned in the fashion of inverse class F in order to achieve more desirable voltage and current waveforms for improved performance. Operational waveforms for several implementations are presented, and efficiency estimates are compared to class-E.

Folded waveguide traveling-wave tube sources for terahertz radiation

Abstract: Microfabricated folded waveguide traveling-wave tubes (TWTs) are potential compact sources of wide-band, high-power terahertz radiation. We present feasibility studies of an oscillator concept using an amplifier with delayed feedback. Simulations of a 560-GHz oscillator and experimental evaluation of the concept at 50 GHz are presented. Additionally, results from various fabrication methods that are under investigation, such as X-ray lithography, electroforming, and molding (LIGA), UV LIGA, and deep reactive ion etching are presented. Observations and measurements are reported on the generation of stable single-frequency oscillation states. On varying the feedback level, the oscillation changes from a stable single-frequency state at the threshold to multifrequency spectra in the overdriven state. Simulation and experimental results on amplifier characterization and dynamics of the regenerative TWT oscillator include spectral evolution and phase stability of the generated frequencies. The results of the experiment are in good agreement with the simulations.

Nonlinear polarization rotation in semiconductor optical amplifiers: theory and application to all-optical flip-flop memories

Abstract: We present a model for polarization-dependent gain saturation in strained bulk semiconductor optical amplifiers. We assume that the polarized optical field can be decomposed into transverse electric and transverse magnetic components that have indirect interaction with each other via the gain saturation. The gain anisotropy due to tensile strain in the amplifier is accounted for by a population imbalance factor. The model is applied to a nonlinear polarization switch, for which results are obtained, that are in excellent agreement with experimental data. Finally, we describe an all-optical flip-flop memory that is based on two coupled nonlinear polarization switches.

A fully matched N-way Doherty amplifier with optimized linearity

Abstract: This paper presents a new fully matched N-way Doherty amplifier. The basic principles of operation and important features are described. For the experimental verification, 2.14-GHz Doherty amplifiers having two-, three-, and four-way structures are implemented using silicon LDMOSFETs and tested using down-link WCDMA signal. The linearity performances of the two-, three-, and four-way Doherty amplifiers are optimized for better efficiency versus linearity by a bias adjustment of the peaking amplifiers. For simultaneously improving the efficiency and linearity to achieve maximum efficiency versus linearity, the gate biases of the peaking amplifiers for the N-way Doherty amplifier are optimized. As a result, the efficiency versus linearity characteristics are drastically improved by N-way extension of the Doherty amplifier.

Low-power, high-modulation-index amplifier for use in battery-powered device

Abstract: An external transmitter circuit drives an implantable neural stimulator having an implanted coil from a primary coil driven by a power amplifier. For efficient power consumption, the transmitter output circuit (which includes the primary coil driven by the power amplifier inductively coupled with the implanted coil) operates as a tuned resonant circuit. When operating as a tuned resonant circuit, it is difficult to modulate the carrier signal with data having sharp rise and fall times without using a high power modulation amplifier. Sharp rise and fall times are needed in order to ensure reliable data transmission. To overcome this difficulty, the present invention includes an output switch that selectively inserts a resistor in the transmitter output coil circuit in order to de-tune the resonant circuit only during those times when data modulation is needed. Such de-tuning allows sharp rise and fall times in the data modulation without the need for using a high power modulation amplifier. Because data modulation is typically needed for only a small percent of the time that a carrier signal is present, it is thus possible using the present invention to achieve reliable data modulation, transmission and reception without having to use a high power modulation amplifier in the transmitter.

Multi-mode amplifier system

Abstract: An amplifier system is provided that switches between a linear mode of operation, an envelope tracking mode of operation and a polar mode of operation. The amplifier system switches between modes of operation based upon a characteristic of an input signal relative to a first threshold level and a second threshold level. A mode selector selects the operation mode by transmitting an amplitude modulated signal plus a variable headroom voltage to a supply terminal of a power amplifier during the envelope tracking mode, an amplitude modulated signal to the supply terminal and phase modulated input signal during the polar mode and a substantially constant amplitude signal to the supply terminal during the linear mode.

A 2.4-GHz 0.18-/spl mu/m CMOS self-biased cascode power amplifier

Abstract: A two-stage self-biased cascode power amplifier in 0.18-/spl mu/m CMOS process for Class-1 Bluetooth application is presented. The power amplifier provides 23-dBm output power with a power-added efficiency (PAE) of 42% at 2.4 GHz. It has a small signal gain of 38 dB and a large signal gain of 31 dB at saturation. This is the highest gain reported for a two-stage design in CMOS at the 0.8-2.4-GHz frequency range. A novel self-biasing and bootstrapping technique is presented that relaxes the restriction due to hot carrier degradation in power amplifiers and alleviates the need to use thick-oxide transistors that have poor RF performance compared with the standard transistors available in the same process. The power amplifier shows no performance degradation after ten days of continuous operation under maximum output power at 2.4-V supply. It is demonstrated that a sliding bias technique can be used to both significantly improve the PAE at mid-power range and linearize the power amplifier. By using the sliding bias technique, the PAE at 16 dBm is increased from 6% to 19%, and the gain variation over the entire power range is reduced from 7 to 0.6 dB.

A robust feedforward compensation scheme for multistage operational transconductance amplifiers with no Miller capacitors

Abstract: A multistage operational transconductance amplifier with a feedforward compensation scheme which does not use Miller capacitors is introduced. The compensation scheme uses the positive phase shift of left-half-plane (LHP) zeroes caused by the feedforward path to cancel the negative phase shift of poles to achieve a good phase margin. A two-stage path increases further the low frequency gain while a feedforward single-stage amplifier makes the circuit faster. The amplifier bandwidth is not compromised by the absence of the traditional pole-splitting effect of Miller compensation, resulting in a high-gain wideband amplifier. The capacitors of a capacitive amplifier using the proposed techniques can be varied more than a decade without significant settling time degradation. Experimental results for a prototype fabricated in an AMI 0.5-/spl mu/m CMOS process show DC gain of around 90 dB and a 1% settling time of 15 ns for a load capacitor of 12 pF. The power supply used is /spl plusmn/1.25 V.

A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC

Abstract: A 10-bit 80-MS/s analog-to-digital converter (ADC) with an area- and power-efficient architecture is described. By sharing an amplifier between two successive pipeline stages, a 10-bit pipeline is realized using just four amplifiers with a separate sample-and-hold block. The proposed feedback signal polarity inverting (FSPI) technique addresses the drawback of the conventional amplifier sharing technique. A wide-swing wide-bandwidth telescopic amplifier and an early comparison technique with a constant delay circuit have been developed to further reduce power consumption. The ADC is implemented in a 0.18-/spl mu/m dual-gate-oxidation CMOS process technology, achieves 72.8-dBc spurious free dynamic range, 57.92-dBc signal-to-noise ratio, 9.29 effective number of bits (ENOB) for a 99-MHz input at full sampling rate, and consumes 69 mW from a 3-V supply. The ADC occupies 1.85 mm/sup 2/.

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-/spl mu/m CMOS

Abstract: A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-/spl mu/m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V.

100-W single-frequency master-oscillator fiber power amplifier.

Abstract: We report the efficient generation of 100-W single-frequency radiation with diffraction-limited beam quality at the 1064-nm wavelength by use of a master-oscillator fiber power-amplifier system, consisting of a diode-pumped monolithic nonplanar ring laser as the master oscillator and an Yb-doped large-mode-area fiber as the power amplifier. The emission spectrum, the intensity noise behavior, and further power-scaling possibilities to the >200-W level, which are determined by the threshold of stimulated Brillouin scattering in the fiber amplifier, are discussed.

Active-feedback frequency-compensation technique for low-power multistage amplifiers

Abstract: An active-feedback frequency-compensation (AFFC) technique for low-power operational amplifiers is presented in this paper. With an active-feedback mechanism, a high-speed block separates the low-frequency high-gain path and high-frequency signal path such that high gain and wide bandwidth can be achieved simultaneously in the AFFC amplifier. The gain stage in the active-feedback network also reduces the size of the compensation capacitors such that the overall chip area of the amplifier becomes smaller and the slew rate is improved. Furthermore, the presence of a left-half-plane zero in the proposed AFFC topology improves the stability and settling behavior of the amplifier. Three-stage amplifiers based on AFFC and nested-Miller compensation (NMC) techniques have been implemented by a commercial 0.8-/spl mu/m CMOS process. When driving a 120-pF capacitive load, the AFFC amplifier achieves over 100-dB dc gain, 4.5-MHz gain-bandwidth product (GBW) , 65/spl deg/ phase margin, and 1.5-V//spl mu/s average slew rate, while only dissipating 400-/spl mu/W power at a 2-V supply. Compared to a three-stage NMC amplifier, the proposed AFFC amplifier provides improvement in both the GBW and slew rate by 11 times and reduces the chip area by 2.3 times without significant increase in the power consumption.

Parametric amplifiers driven by two pump waves

Abstract: Parametric amplifiers (PAs) are well-suited for optical communication systems. Not only can PAs provide high gain for arbitrary signal wavelengths, they can also conjugate the signals and convert their wavelengths. The four-sideband model of parametric amplifiers driven by two pump waves will be reviewed and used to describe the conditions required to produce broad-bandwidth gain. The flexibility of the two-pump architecture allows it to produce gain that is nearly independent of the signal polarization, and idlers whose spectral widths are comparable to that of the signal.

AC-coupled front-end for biopotential measurements

Abstract: AC coupling is essential in biopotential measurements. Electrode offset potentials can be several orders of magnitude larger than the amplitudes of the biological signals of interest, thus limiting the admissible gain of a dc-coupled front end to prevent amplifier saturation. A high-gain input stage needs ac input coupling. This can be achieved by series capacitors, but in order to provide a bias path, grounded resistors are usually included, which degrade the common mode rejection ratio (CMRR). This paper proposes a novel balanced input ac-coupling network that provides a bias path without any connection to ground, thus resulting in a high CMRR. The circuit being passive, it does not limit the differential dc input voltage. Furthermore, differential signals are ac coupled, whereas common-mode voltages are dc coupled, thus allowing the closed-loop control of the dc common mode voltage by means of a driven-right-leg circuit. This makes the circuit compatible with common-mode dc shifting strategies intended for single-supply biopotential amplifiers. The proposed circuit allows the implementation of high-gain biopotential amplifiers with a reduced number of parts, thus resulting in low power consumption. An electrocardiogram amplifier built according to the proposed design achieves a CMRR of 123 dB at 50 Hz.

120-GHz wireless link using photonic techniques for generation, modulation, and emission of millimeter-wave signals

Abstract: We present a wireless link system that uses millimeter-wave (MMW) photonic techniques. The photonic transmitter in the wireless link consists of an optical 120-GHz MMW generator, an optical modulator, and a high-power photonic MMW emitter. A uni-traveling carrier photodiode (UTC-PD) was used as the photonic emitter in order to eliminate electronic MMW amplifiers. We evaluated the dependence of UTC-PD output power on its transit-time limited bandwidth and its CR-time constant limited bandwidth, and employed a UTC-PD with the highest output power for the photonic emitter. As for the MMW generation, we developed a 120-GHz optical MMW generator that generates a pulse train and one that generates a sinusoidal signal. The UTC-PD output power generated by a narrow pulse train was higher than that generated by sinusoidal signals under the same average optical power condition, which contributes to reducing the photocurrent of the photonic emitter. We have experimentally demonstrated that the photonic transmitter can transmit data at up to 3.0 Gb/s. The wireless link using the photonic transmitter can be applied to optical gigabit Ethernet signals.

Polar modulation transmitter

Abstract: A polar modulation transmitter circuit provides reduced ACPR in its output signal by controlling the relative delay between its envelope and phase modulation operations based on direct or indirect feedback measurement the output signal's ACPR. Such measurement and associated control may be based on a delay controller that includes an ACPR measurement circuit and a delay control circuit. Additionally, or alternatively, the polar modulation transmitter circuit provides a greatly extended transmit power control range by using a staged amplifier circuit that includes a driver amplifier circuit operating in combination with a power amplifier circuit to impart desired envelope modulation. In an exemplary embodiment, the driver amplifier circuit is implemented as differential transistor pairs responsive to tail current modulation. As such, the driver amplifier circuit is suited in particular for economical and space saving integration within a transmitter or transceiver integrated circuit (IC).

Phase-controlled amplification of few-cycle laser pulses

Abstract: Intense ultrashort waveforms of light that can be produced with an exactly predetermined electromagnetic field are essential in a number of applications of extreme nonlinear optics, most prominently in laser-driven sources of high-energy attosecond radiation. Field reproducibility in each laser shot requires stabilization of the carrier-envelope phase. The authors analyze different schemes of phase-stable pulse amplification and identify constraints limiting the precision with which the phase can be maintained. Next, they describe a phase-stabilized laser system based on a 20-fs multipass Ti:sapphire amplifier supplemented with a fiber compression stage for producing pulses in the few-cycle regime. It is shown that the amplifier introduces only a slow millihertz phase drift and, therefore, can be seeded by a standard phase-stabilized oscillator. This residual phase drift is assigned primarily to the beam pointing instability and can be precompensated in the phase-control loop of the seed oscillator using a feedback signal from a phase detector placed in the amplifier output. The phase stability of the resultant 5-fs 400-/spl mu/J pulses at a 1-kHz repetition rate is subsequently independently verified by higher order harmonic generation, in which different carrier-envelope phase settings are shown, both theoretically and experimentally, to produce distinctly different spectral shapes of the XUV radiation. From a series of such spectral patterns, the authors succeed in calibrating the value of the carrier envelope phase (with a /spl plusmn//spl pi/ ambiguity), which in turn allows them to fully characterize the temporal structure of the electric field of the laser pulses. The estimated precision of the phase control on the XUV target is better than /spl pi//5, which reduces the timing jitter between the driving laser pulse and the XUV bursts to /spl sim/ 250 as and opens the way to generate stable isolated attosecond pulses.

Amorphous silicon active pixel sensor readout circuit for digital imaging

Abstract: The most widely used architecture in large-area amorphous silicon (a-Si) flat panel imagers is a passive pixel sensor (PPS), which consists of a detector and a readout switch. While the PPS has the advantage of being compact and amenable toward high-resolution imaging, reading small PPS output signals requires external column charge amplifiers that produce additional noise and reduce the minimum readable sensor input signal. This work presents a current-mediated amorphous silicon active pixel readout circuit that performs on-pixel amplification of noise-vulnerable sensor input signals to minimize the effect of external readout noise sources associated with "off-chip" charge amplifiers. Results indicate excellent small-signal linearity along with a high, and programmable, charge gain. In addition, the active pixel circuit shows immunity to shift in threshold voltage that is characteristic of a-Si devices. Preliminary circuit noise results and analysis appear promising for its use in noise-sensitive, large-area, medical diagnostic imaging applications such as digital fluoroscopy.

An integrated 200-W class-D audio amplifier

Abstract: An integrated stereo class-D audio power amplifier realized in a silicon-on-insulator (SOI)-based BCD technology is presented. The amplifier is capable of delivering 2/spl times/100 W in two 4-/spl Omega/ loads at a supply voltage of 60 V. A second-order feedback loop is used to suppress supply ripple and pulse-shape errors in the switching power stage. The limiting factor in the performance of any class-D amplifiers is the quality of the switching power stage. A high-speed low-current levelshifter and a robust deadtime control arrangement are proposed that enable the realization of a robust high-quality switching power stage. Some practical issues with respect to robustness and electromagnetic compatibility are discussed.

Semiconductor memory device capable of generating internal data read timing precisely

Abstract: Dummy cells are divided into a plurality of divided dummy columns, and divided dummy bit lines are arranged corresponding to the divided dummy columns. These divided dummy bit lines are provided with dummy sense amplifiers that drive a sense control line transmitting a sense enable signal activating a sense amplifier. A faster activation timing of the sense amplifier can be achieved.

A 0.6-22-GHz broadband CMOS distributed amplifier

Abstract: A CMOS distributed amplifier (DA) covering 0.6 to 22 GHz is presented in this paper. Cascode gain cells and m-derived matching sections are used to enhance the gain and bandwidth performance. The DA chip achieves measured gain of 7.3 /spl plusmn/ 0.8 dB with chip area of 0.9 /spl times/ 1.5 mm/sup 2/ including testing pads. The amplifier was fabricated in a standard 0.18-/spl mu/m CMOS technology and demonstrated the highest frequency and bandwidth of operation among previously reported amplifiers using regular CMOS processes to date.

NINO: an ultrafast low-power front-end amplifier discriminator for the time-of-flight detector in the ALICE experiment

Abstract: An ultrafast front-end preamplifier-discriminator chip called NINO has been developed for use in the ALICE time-of-flight detector. The chip has eight channels. Each channel is designed with an amplifier with less than 1-ns peaking time, a discriminator with a minimum detection threshold of 10 fC and an output stage. The output pulse has minimum time jitter (less than 25 ps) on the front edge, and the pulsewidth is dependent of the input signal charge. Each channel consumes 27 mW, and the eight channels fit in a 2/spl times/4 mm/sup 2/ ASIC processed in IBM 0.25-/spl mu/m CMOS technology.

Multi-mode multi-amplifier architecture

Abstract: An amplification architecture or system is provided having a multiple amplifier system that switches modes of operation between operation in a component mode and a composite mode based on a characteristic of an input signal relative to a threshold level. In the component mode, the components of the input signal are employed to different terminals of the multiple amplifier system that provide a reconstructed amplified representation of the input signal. In the composite mode, the input signal is amplified to provide an amplified representation of the input signal.