scispace - formally typeset
Search or ask a question

Showing papers on "Amplifier published in 2004"


Journal ArticleDOI
TL;DR: In this article, a feed-forward noise-canceling technique is proposed to cancel the noise and distortion contributions of the matching device, which allows for designing wide-band impedance-matching amplifiers with noise figure (NF) well below 3 dB.
Abstract: Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In contrast, this paper presents a feedforward noise-canceling technique, which allows for simultaneous noise and impedance matching, while canceling the noise and distortion contributions of the matching device. This allows for designing wide-band impedance-matching amplifiers with NF well below 3 dB, without suffering from instability issues. An amplifier realized in 0.25-/spl mu/m standard CMOS shows NF values below 2.4 dB over more than one decade of bandwidth (i.e., 150-2000 MHz) and below 2 dB over more than two octaves (i.e., 250-1100 MHz). Furthermore, the total voltage gain is 13.7 dB, the -3-dB bandwidth is from 2 MHz to 1.6 GHz, the IIP2 is +12 dBm, and the IIP3 is 0 dBm. The LNA drains 14 mA from a 2.5-V supply and the die area is 0.3/spl times/0.25 mm/sup 2/.

749 citations


Journal ArticleDOI
TL;DR: An ultrawideband 3.1-10.6-GHz low-noise amplifier employing an input three-section band-pass Chebyshev filter using a 0.18-/spl mu/m CMOS process achieves a power gain of 9.3 dB with an input match of -10 dB over the band.
Abstract: An ultrawideband 3.1-10.6-GHz low-noise amplifier employing an input three-section band-pass Chebyshev filter is presented. Fabricated in a 0.18-/spl mu/m CMOS process, the IC prototype achieves a power gain of 9.3 dB with an input match of -10 dB over the band, a minimum noise figure of 4 dB, and an IIP3 of -6.7 dBm while consuming 9 mW.

714 citations


Journal ArticleDOI
TL;DR: Theoretical and experimental results are presented that establish the value of parallel excitation with a transmit coil array in accelerating excitation and managing RF power deposition and suggest that by exploiting the localization characteristics of the coils, an orchestrated play of shorter RF pulses can achieve desired excitation profiles faster without adding strains to gradients.
Abstract: Theoretical and experimental results are presented that establish the value of parallel excitation with a transmit coil array in accelerating excitation and managing RF power deposition. While a 2D or 3D excitation pulse can be used to induce a multidimensional transverse magnetization pattern for a variety of applications (e.g., a 2D localized pattern for accelerating spatial encoding during signal acquisition), it often involves the use of prolonged RF and gradient pulses. Given a parallel system that is composed of multiple transmit coils with corresponding RF pulse synthesizers and amplifiers, the results suggest that by exploiting the localization characteristics of the coils, an orchestrated play of shorter RF pulses can achieve desired excitation profiles faster without adding strains to gradients. A closed-form design for accelerated multidimensional excitations is described for the small-tip-angle regime, and its suppression of interfering aliasing lobes from coarse excitation k-space sampling is interpreted based on an analogy to sensitivity encoding (SENSE). With or without acceleration, the results also suggest that by taking advantage of the extra degrees of freedom inherent in a parallel system, parallel excitation provides better management of RF power deposition while facilitating the faithful production of desired excitation profiles. Sample accelerated and specific absorption rate (SAR)-reduced excitation pulses were designed in this study, and evaluated in experiments.

640 citations


Journal ArticleDOI
TL;DR: In this article, four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology are reviewed and analyzed: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-consistency with SNIM (PCSNIM) techniques.
Abstract: This paper reviews and analyzes four reported low-noise amplifier (LNA) design techniques applied to the cascode topology based on CMOS technology: classical noise matching, simultaneous noise and input matching (SNIM), power-constrained noise optimization, and power-constrained simultaneous noise and input matching (PCSNIM) techniques. Very simple and insightful sets of noise parameter expressions are newly introduced for the SNIM and PCSNIM techniques. Based on the noise parameter equations, this paper provides clear understanding of the design principles, fundamental limitations, and advantages of the four reported LNA design techniques so that the designers can get the overall LNA design perspective. As a demonstration for the proposed design principle of the PCSNIM technique, a very low-power folded-cascode LNA is implemented based on 0.25-/spl mu/m CMOS technology for 900-MHz Zigbee applications. Measurement results show the noise figure of 1.35 dB, power gain of 12 dB, and input third-order intermodulation product of -4dBm while dissipating 1.6 mA from a 1.25-V supply (0.7 mA for the input NMOS transistor only). The overall behavior of the implemented LNA shows good agreement with theoretical predictions.

542 citations


Journal ArticleDOI
TL;DR: In this paper, the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage was investigated for a latch-type voltage sense amplifier with a high-impedance differential input stage.
Abstract: A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage. The input DC level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input DC bias voltage. A figure of merit indicates that an input dc level of 0.7 V/sub DD/ is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input DC voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.

450 citations


Journal ArticleDOI
06 Jun 2004
TL;DR: In this paper, a modified derivative-superposition (DS) method was proposed to increase the maximum IIP3 at RF frequencies, which was used in a 0.25mum Si CMOS low-noise amplifier (LNA) designed for cellular code-division multiple access receivers.
Abstract: Intermodulation distortion in field-effect transistors (FETs) at RF frequencies is analyzed using the Volterra-series analysis. The degrading effect of the circuit reactances on the maximum IIP3 in the conventional derivative-superposition (DS) method is explained. The noise performance of this method is also analyzed and the effect of the subthreshold biasing of one of the FETs on the noise figure (NF) is shown. A modified DS method is proposed to increase the maximum IIP3 at RF. It was used in a 0.25-mum Si CMOS low-noise amplifier (LNA) designed for cellular code-division multiple-access receivers. The LNA achieved +22-dBm IIP3 with 15.5-dB gain, 1.65-dB NF, and 9.3 mA@2.6-V power consumption

366 citations


Journal ArticleDOI
13 Sep 2004
TL;DR: In this paper, a very low power interface IC used in implantable pacemaker systems is presented, which contains amplifiers, filters, ADCs, battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control.
Abstract: Low power consumption is crucial for medical implant devices. A single-chip, very-low-power interface IC used in implantable pacemaker systems is presented. It contains amplifiers, filters, ADCs, battery management system, voltage multipliers, high voltage pulse generators, programmable logic and timing control. A few circuit techniques are proposed to achieve nanopower circuit operations within submicron CMOS process. Subthreshold transistor designs and switched-capacitor circuits are widely used. The 200 k transistor IC occupies 49 mm/sup 2/, is fabricated in a 0.5-/spl mu/m two-poly three-metal multi-V/sub t/ process, and consumes 8 /spl mu/W.

347 citations


Journal ArticleDOI
TL;DR: In this paper, an 8-channel amplifier and discriminator chip has been developed to exploit the excellent timing properties of the multigap resistive plate chamber (MRPC), which is fabricated with 0.25 μ m CMOS technology.
Abstract: For the full exploitation of the excellent timing properties of the Multigap Resistive Plate Chamber (MRPC), front-end electronics with special characteristics are needed. These are (a) differential input, to profit from the differential signal from the MRPC (b) a fast amplifier with less than 1 ns peaking time and (c) input charge measurement by Time-Over-Threshold for slewing correction. An 8-channel amplifier and discriminator chip has been developed to match these requirements. This is the NINO ASIC, fabricated with 0.25 μ m CMOS technology. The power requirement at 40 mW/channel is low. Results on the performance of the MRPCs using the NINO ASIC are presented. Typical time resolution σ of the MRPC system is in the 50 ps range, with an efficiency of 99.9 % .

343 citations


Proceedings Article
01 Jan 2004
TL;DR: In this paper, a SiGe amplifier with on-chip matching network spanning 3-10 GHz was presented, achieving 21dB peak gain, 2.5dB noise figure, and -1dBm input IP3 at 5 GHz, with a 10-mA bias current.
Abstract: Reactive matching is extended to wide bandwidths using the impedance property of LC-ladder filters. In this paper, we present a systematic method to design wideband low-noise amplifiers. An SiGe amplifier with on-chip matching network spanning 3-10 GHz delivers 21-dB peak gain, 2.5-dB noise figure, and -1-dBm input IP3 at 5 GHz, with a 10-mA bias current.

342 citations


Journal ArticleDOI
TL;DR: In this article, a SiGe amplifier with on-chip matching network spanning 3-10 GHz was presented, achieving 21dB peak gain, 2.5dB noise figure, and -1dBm input IP3 at 5 GHz, with a 10-mA bias current.
Abstract: Reactive matching is extended to wide bandwidths using the impedance property of LC-ladder filters. In this paper, we present a systematic method to design wideband low-noise amplifiers. An SiGe amplifier with on-chip matching network spanning 3-10 GHz delivers 21-dB peak gain, 2.5-dB noise figure, and -1-dBm input IP3 at 5 GHz, with a 10-mA bias current.

335 citations


Journal ArticleDOI
TL;DR: Pulsed microwave reflection measurements on nanofabricated Al junctions show that actual devices attain the performance predicted by theory, and the absence of on-chip dissipation is shown.
Abstract: We have constructed a new type of amplifier whose primary purpose is the readout of superconducting quantum bits. It is based on the transition of a rf-driven Josephson junction between two distinct oscillation states near a dynamical bifurcation point. The main advantages of this new amplifier are speed, high sensitivity, low backaction, and the absence of on-chip dissipation. Pulsed microwave reflection measurements on nanofabricated Al junctions show that actual devices attain the performance predicted by theory.

Journal ArticleDOI
Tae Wook Kim1, Bonkee Kim, Kwyro Lee1
TL;DR: In this article, a high-level linear receiver RF front-end adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistors in parallel (multiple gated transistor, or MGTR), combined with some additional circuit techniques are reported.
Abstract: Highly linear receiver RF front-end adopting MOSFET transconductance linearization by linearly superposing several common-source FET transistors in parallel (multiple gated transistor, or MGTR), combined with some additional circuit techniques are reported. In MGTR circuitry, linearity is improved by using transconductance linearization which can be achieved by canceling the negative peak value of g/sub m/'' of the main transistor with the positive one in the auxiliary transistor having a different size and gate drive combined in parallel. This enhancement, however, is limited by the distortion originated from the combined influence of g/sub m/' and harmonic feedback, which can greatly be reduced by the cascoding MGTR output for the amplifier and by the tuned load for the mixer. Experimental results designed using the above techniques show IIP/sub 3/ improvements at given power consumption by as much as 10 dB for CMOS low-noise amplifier at 900 MHz and 7 dB for Gilbert cell mixer at 2.4 GHz without sacrificing other features such as gain and noise figure.

Journal ArticleDOI
TL;DR: The performance of oversampling before applying PAR reduction is analyzed, and results show that this is necessary to sufficiently handle the analog PAR problem, and the new active-set method proposed here converges very quickly toward a minimum-PAR solution at a lower computational cost.
Abstract: Common to all orthogonal frequency division multiplexing (OFDM) systems is a large peak-to-average-power ratio (PAR), which can lead to low power efficiency and nonlinear distortion at the transmit power amplifier. Tone reservation uses other unused or reserved tones to design a peak-cancelling signal that lowers the PAR of a transmit OFDM block. In contrast to previous methods, the new active-set method proposed here converges very quickly toward a minimum-PAR solution at a lower computational cost. An efficient real-baseband algorithm is well suited for discrete multitone (DMT) modulation over twisted-pair copper wiring, where some subchannels may have an insufficient SNR to reliably send data. The real PAR problem occurs in the analog signal before the power amplifier, and results focus on this figure of merit. The performance of oversampling before applying PAR reduction is analyzed, and results show that this is necessary to sufficiently handle the analog PAR problem. An extension of the real-baseband technique can be applied to complex-baseband signals to help reduce PAR in wireless and broadcast systems. By sacrificing 11 out of 256 OFDM tones (4.3%) for tone reservation, over 3 dB of analog PAR reduction can be obtained for a wireless system.

Journal ArticleDOI
TL;DR: In this article, a CMOS capacitive sensing amplifier for a monolithic MEMS accelerometer fabricated by post-CMOS surface micromachining is described, which employs capacitance matching with optimal transistor sizing to minimize sensor noise floor.
Abstract: This paper describes a CMOS capacitive sensing amplifier for a monolithic MEMS accelerometer fabricated by post-CMOS surface micromachining. This chopper stabilized amplifier employs capacitance matching with optimal transistor sizing to minimize sensor noise floor. Offsets due to sensor and circuit are reduced by ac offset calibration and dc offset cancellation based on a differential difference amplifier (DDA). Low-duty-cycle periodic reset is used to establish robust dc bias at the sensing electrodes with low noise. This work shows that continuous-time voltage sensing can achieve lower noise than switched-capacitor charge integration for sensing ultra-small capacitance changes. A prototype accelerometer integrated with this circuit achieves 50-/spl mu/g//spl radic/Hz acceleration noise floor and 0.02-aF//spl radic/Hz capacitance noise floor while chopped at 1 MHz.

Journal ArticleDOI
TL;DR: In this paper, the first 24 GHz CMOS front-end in a 0.18/spl mu/m process was reported, which consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz.
Abstract: This paper reports the first 24-GHz CMOS front-end in a 0.18-/spl mu/m process. It consists of a low-noise amplifier (LNA) and a mixer and downconverts an RF input at 24 GHz to an IF of 5 GHz. It has a power gain of 27.5 dB and an overall noise figure of 7.7 dB with an input return loss, S/sub 11/ of -21 dB consuming 20 mA from a 1.5-V supply. The LNA achieves a power gain of 15 dB and a noise figure of 6 dB on 16 mA of dc current. The LNA's input stage utilizes a common-gate with resistive feedthrough topology. The performance analysis of this topology predicts the experimental results with good accuracy.

Journal ArticleDOI
TL;DR: In this article, a transimpedance amplifier was realized in a 0.6/spl mu/m digital CMOS technology for Gigabit Ethernet applications, which exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as Si Bipolar or GaAs MESFET.
Abstract: A transimpedance amplifier (TIA) has been realized in a 0.6-/spl mu/m digital CMOS technology for Gigabit Ethernet applications. The amplifier exploits the regulated cascode (RGC) configuration as the input stage, thus achieving as large effective input transconductance as that of Si Bipolar or GaAs MESFET. The RGC input configuration isolates the input parasitic capacitance including photodiode capacitance from the bandwidth determination better than common-gate TIA. Test chips were electrically measured on a FR-4 PC board, demonstrating transimpedance gain of 58 dB/spl Omega/ and -3-dB bandwidth of 950 MHz for 0.5-pF photodiode capacitance. Even with 1-pF photodiode capacitance, the measured bandwidth exhibits only 90-MHz difference, confirming the mechanism of the RGC configuration. In addition, the noise measurements show average noise current spectral density of 6.3 pA//spl radic/(Hz) and sensitivity of -20-dBm for a bit-error rate of 10/sup -12/. The chip core dissipates 85 mW from a single 5-V supply.

Journal Article
TL;DR: The theoretical fundamentals of fiber-based optical parametric amplifiers (OPA) are reviewed in this article, and their applications are discussed in the end the future research aspects are expected.
Abstract: The theoretical fundamentals of fiber-based optical parametric amplifiers(OPA) are reviewed,and their applications are discussed in this paper.In the end the future research aspects are expected.

Patent
Vlad Grigore1
16 Sep 2004
TL;DR: In this article, the authors proposed a DC-DC converter that has a switch mode part for coupling between a DC source and a load, and a linear mode part coupled in parallel with the switch-mode part between the source and the load.
Abstract: In one aspect this invention provides a DC-DC converter that has a switch mode part for coupling between a DC source and a load, the switch mode part providing x amount of output power; and that further has a linear mode part coupled in parallel with the switch mode part between the DC source and the load, the linear mode part providing y amount of output power, where x is preferably greater than y, and the ratio of x to y may be optimized for particular application constraints. In a further aspect there is a radio frequency (RF) transmitter (TX) for coupling to an antenna, where the TX has a polar architecture having an amplitude modulation (AM) path coupled to a power supply of a power amplifier (PA) and a phase modulation (PM) path coupled to an input of the PA, where the power supply includes the switch mode part for coupling between a battery and the PA and the linear mode part coupled in parallel with the switch mode part between the battery and the PA.

Proceedings Article
01 Jan 2004
TL;DR: In this article, series-resonant vibrating micromechanical resonator oscillators are demonstrated using a custom-designed single-stage zero-phase-shift sustaining amplifier together with planar-processed micromachanical resonators with quality factors Q in the thousands that differ mainly in their power-handling capacities.
Abstract: Series-resonant vibrating micromechanical resonator oscillators are demonstrated using a custom-designed single-stage zero-phase-shift sustaining amplifier together with planar-processed micromechanical resonator variants with quality factors Q in the thousands that differ mainly in their power-handling capacities. The resonator variants include two 40-μm-long 10-MHz clamped-clamped-beam (CC-beam) resonators, one of them much wider than the other so as to allow larger power-handling capacity, and a 64-μm-diameter 60-MHz disk resonator that maximizes both Q and power handling among the resonators tested. Trade-offs between Q and power handling are seen to be most important in setting the close-to-carrier and far-from-carrier phase noise behavior of each oscillator, although such parameters as resonant frequency and motional resistance are also important. With a 10× higher power handling capability than the wide-width CC-beam resonator, a comparable series motional resistance, and a 45 x higher Q of 48 000, the 60-MHz wine glass resonator reference oscillator exhibits a measured phase noise of -110 dBc/Hz at 1-kHz offset, and -132 dBc/Hz at far-from-carrier offsets. Dividing down to 10 MHz for fair comparison with a common conventional standard, this oscillator achieves a phase noise of -125 dBc/Hz at 1-kHz offset, and -147 dBc/Hz at far-from-carrier offsets.

Journal ArticleDOI
TL;DR: In this paper, a design principle for very low-voltage analog signal processing in CMOS technologies is presented, based on the use of quasi-floating gate (QFG) MOS transistors.
Abstract: A novel design principle for very low-voltage analog signal processing in CMOS technologies is presented. It is based on the use of quasi-floating gate (QFG) MOS transistors. Similar to multiple input floating gate (MIFG) MOS transistors, a weighted averaging of the inputs accurately controlled by capacitance ratios can be obtained, which is the basic operating principle. Nevertheless, issues often encountered in MIFG structures, such as the initial charge trapped in the floating gates or the gain-bandwidth product degradation, are not present in QFG configurations. Several CMOS circuit realizations using open- and closed-loop topologies, have been designed. They include analog switches, mixers, programmable-gain amplifiers, track and hold circuits, and digital-to-analog converters. All these circuits have been experimentally verified, confirming the usefulness of the proposed technique for very low-voltage applications.

Journal ArticleDOI
TL;DR: In this paper, a low-pass filter component values are used to improve the bandwidth of a CMOS transimpedance amplifier, which achieves 3 dB bandwidth of 9.2 GHz in the presence of a 0.5-pF photodiode capacitance.
Abstract: A technique for bandwidth enhancement of a given amplifier is presented. Adding several interstage passive matching networks enables the control of transfer function and frequency response behavior. Parasitic capacitances of cascaded gain stages are isolated from each other and absorbed into passive networks. A simplified design procedure, using well-known low-pass filter component values, is introduced. To demonstrate the feasibility of the method, a CMOS transimpedance amplifier (TIA) is implemented in a 0.18-/spl mu/m BiCMOS technology. It achieves 3 dB bandwidth of 9.2 GHz in the presence of a 0.5-pF photodiode capacitance. This corresponds to a bandwidth enhancement ratio of 2.4 over the amplifier without the additional passive networks. The transresistance gain is 54 dB/spl Omega/, while drawing 55 mA from a 2.5-V supply. The input sensitivity of the TIA is -18 dBm for a bit error rate of 10/sup -12/.

Patent
28 Oct 2004
TL;DR: In this article, a switched resonant power amplifier for ultrasonic transducers is described, which includes an amplifier that receives and processes a driver output signal for generating a drive signal that is provided to an ultrasonic device for controlling output of the ultrasonic devices.
Abstract: A switched resonant power amplifier system for ultrasonic transducers is disclosed. The system includes an amplifier that receives and processes a driver output signal for generating a drive signal that is provided to an ultrasonic device for controlling output of the ultrasonic device. An output control circuit receives and processes a signal related to a feedback signal generated by the ultrasonic device and a divider reference signal, and generates a compensated clock signal that is adjusted for at least one of phase and frequency differences between the received feedback signal and the divider reference signal. A compensated drive circuit receives and processes the compensated clock signal for generating the divider reference signal, and for generating the driver output signal.

Proceedings ArticleDOI
30 Nov 2004
TL;DR: A simple, intuitive, voltage divider model is introduced to analyze the PSR of linear regulators, from which design guidelines for obtaining high PSR performance are derived.
Abstract: Linear regulators are critical analog blocks that shield a system from fluctuations in supply rails and the importance of determining their power supply rejection (PSR) performance is magnified in SoC systems, given their inherently noisy environments. In this work, a simple, intuitive, voltage divider model is introduced to analyze the PSR of linear regulators, from which design guidelines for obtaining high PSR performance are derived. The PSR of regulators that use PMOS output stages for low drop-out (LDO), crucial for modern low-voltage systems, is enhanced by error amplifiers which present a supply-correlated ripple at the gate of the PMOS pass device. On the other hand, amplifiers that suppress the supply ripple at their output are optimal for NMOS output stages since the source is now free from output ripple. A better PSR bandwidth, at the cost of dc PSR, can be obtained by interchanging the amplifiers in the two cases. It has also been proved that the dc PSR, its dominant frequency breakpoint (where performance starts to degrade), and three subsequent breakpoints are determined by the dc open-loop gain, error amplifier bandwidth, unity-gain frequency (UGF) of the system, output pole, and ESR zero, respectively. These results were verified with SPICE simulations using BSIM3 models for the TSMC 0.35 /spl mu/m CMOS process from MOSIS.

Journal ArticleDOI
TL;DR: In this article, a high-performance all-solid-state broad-band frequency multiplier chain at 1500 GHz was presented, which uses four cascaded planar Schottky-barrier varactor doublers.
Abstract: We report the results of a high-performance all-solid-state broad-band frequency multiplier chain at 1500 GHz, which uses four cascaded planar Schottky-barrier varactor doublers. The multipliers are driven by monolithic-microwave integrated-circuit-based high electron-mobility transistor power amplifiers around 95 GHz with 100-150 mW of pump power. The design incorporates balanced doublers utilizing novel substrateless and membrane device fabrication technologies, achieving low-loss broad-band multipliers working in the terahertz range. For a drive power of approximately 100 mW in the 88-99-GHz range, the doublers achieved room-temperature peak efficiencies of approximately 30% at the 190-GHz stage, 20% at 375 GHz, 9% at 750 GHz, and 4% at the 1500-GHz stage. When the chain was cooled to 120 K, approximately 40 /spl mu/W of peak output power was measured for 100 mW of input pump power.

Journal ArticleDOI
TL;DR: It is shown that low frequency noise sources, such as seed noise, pump noise, and detuning fluctuations, present in optical parametric amplifiers, have negligible effect on squeezing produced by a below-threshold OPO.
Abstract: We demonstrate the generation of broadband continuous-wave optical squeezing from 280 Hz-100 kHz using a below-threshold optical parametric oscillator (OPO). The squeezed state phase was controlled using a noise locking technique. We show that low frequency noise sources, such as seed noise, pump noise, and detuning fluctuations, present in optical parametric amplifiers, have negligible effect on squeezing produced by a below-threshold OPO. This low frequency squeezing is ideal for improving the sensitivity of audio frequency measuring devices such as gravitational-wave detectors.

Journal ArticleDOI
TL;DR: In this paper, a new approach for the analysis of the efficiency and linearity of Chireix-outphasing combiners is presented, taking into account, in an explicit manner, the effect of impedance mismatch between the amplifiers and the lossless combining structure.
Abstract: A new approach for the analysis of the efficiency and linearity of Chireix-outphasing combiners is presented. The approach takes into account, in an explicit manner, the effect of impedance mismatch between the amplifiers and the lossless combining structure. It is shown that the impedance mismatch leads to new expressions for the output voltages from both branches of the amplifier. These expressions explain the origin of the lack of linearity reported in the literature for the Chireix architecture and lead to a new expression for the instantaneous efficiency of a Chireix combiner. Various simulations using a commercial simulator are performed and their results are compared to those predicted by the derived equations. A quasi-exact agreement between the simulator and derived equations is found for all simulations conducted, including voltage expressions, linearity analysis, and instantaneous and average efficiency calculations for a code-division multiple-access signal. The impact of combiner parameters on its linearity and efficiency is also studied.

Journal ArticleDOI
TL;DR: In this article, a superconducting quantum interference device (SQUID) multiplexer operated at microwave frequencies is described, where the outputs of multiple SQUIDs are simultaneously modulated at different frequencies and summed into the input of one high electron mobility transistor (HEMT).
Abstract: We describe a superconducting quantum interference device (SQUID) multiplexer operated at microwave frequencies. The outputs of multiple SQUIDs are simultaneously modulated at different frequencies and summed into the input of one high electron mobility transistor (HEMT). The large bandwidth and dynamic range provided by HEMT amplifiers should make it possible to frequency-division multiplex a large number of SQUIDs in one output coaxial cable. We measure low SQUID noise (∼0.5μΦ0∕Hz at 4K) and demonstrate the multiplexed readout of two direct current (dc) SQUIDs at different resonant frequencies. In this work, dc SQUIDs are used, but this approach is equally applicable to radio-frequency SQUIDs.

Journal ArticleDOI
TL;DR: In this paper, the authors proposed a new simplified Volterra series based model for RF power amplifiers by employing a "near-diagonality" pruning algorithm to remove the coefficients which are very small, or else not sensitive to the output error.
Abstract: Behavioral modeling techniques provide a convenient and efficient means to predict system-level performance without the computational complexity of full circuit simulation or physics-level analysis of nonlinear systems, thereby significantly speeding up the analysis process. General Volterra series based models have been successfully applied for radio frequency (RF) power amplifier (PA) behavioral modeling, but their high complexity tends to limit their applications to "weakly" nonlinear systems. To model a PA with strong nonlinearities and long memory effects, for example, the general Volterra model involves a great number of coefficients. In this letter, we propose a new simplified Volterra series based model for RF power amplifiers by employing a "near-diagonality" pruning algorithm to remove the coefficients which are very small, or else not sensitive to the output error, therefore dramatically reducing the complexity of the behavioral model.

Journal ArticleDOI
TL;DR: In this article, an inductive power system is presented, capable of remotely powering implantable monitoring and stimulating devices, with an efficiency of 36% over a distance of 3 cm. Optimisation of the power transfer efficiency and the misalignment tolerance was obtained using a self developed design tool.
Abstract: An inductive powering system is presented, capable of remotely powering implantable monitoring and stimulating devices. The system is capable of delivering at least 50 mW, with an efficiency of 36% over a distance of 3 cm. The power transfer frequency is 700 kHz. Optimisation of the power transfer efficiency and the misalignment tolerance was obtained using a self-developed design tool. Bi-directional data-transmission is integrated in the system: amplitude modulation is applied for the downlink transmission, absorption modulation for the uplink transmission. Our new system is capable of transmitting data at a maximal bit rate of 60,000 bits/s.

Patent
05 Feb 2004
TL;DR: In this article, a memory device having banks of sense amplifiers comprising two types of senses amplifiers is described, where a first driver used to activate the first sense amplifier is embedded into a first bank, and a second driver used by the second sense amplifier to activate a second type of senses amplifier is inserted into a second bank.
Abstract: A memory device having banks of sense amplifiers comprising two types of sense amplifiers. A first driver used to activate the first type of sense amplifier is embedded into a first bank. A second driver used to activate a second type of sense amplifier is embedded into a second bank. This alternating physical placement of the first and second sense amplifier drivers within respective banks is repeated throughout the device. This alternating physical arrangement frees up the gaps and mini-gaps for other functions, reduces the buses used for sense amplifier activation signals and allows large drivers to be used, which improves the operation of the sense amplifiers and the device itself.