Showing papers on "Amplifier published in 2006"
TL;DR: This paper relates the general Volterra representation to the classical Wiener, Hammerstein, Wiener-Hammerstein, and parallel Wiener structures, and describes some state-of-the-art predistortion models based on memory polynomials, and proposes a new generalizedMemory polynomial that achieves the best performance to date.
Abstract: Conventional radio-frequency (RF) power amplifiers operating with wideband signals, such as wideband code-division multiple access (WCDMA) in the Universal Mobile Telecommunications System (UMTS) must be backed off considerably from their peak power level in order to control out-of-band spurious emissions, also known as "spectral regrowth." Adapting these amplifiers to wideband operation therefore entails larger size and higher cost than would otherwise be required for the same power output. An alternative solution, which is gaining widespread popularity, is to employ digital baseband predistortion ahead of the amplifier to compensate for the nonlinearity effects, hence allowing it to run closer to its maximum output power while maintaining low spectral regrowth. Recent improvements to the technique have included memory effects in the predistortion model, which are essential as the bandwidth increases. In this paper, we relate the general Volterra representation to the classical Wiener, Hammerstein, Wiener-Hammerstein, and parallel Wiener structures, and go on to describe some state-of-the-art predistortion models based on memory polynomials. We then propose a new generalized memory polynomial that achieves the best performance to date, as demonstrated herein with experimental results obtained from a testbed using an actual 30-W, 2-GHz power amplifier
1,305 citations
Book•
01 May 2006
TL;DR: The second edition of the Artech House book, RF Power Amplifiers for Wireless Communications as discussed by the authors, provides a comprehensive, practical, and up-to-date understanding of how to tackle a power amplifier design with confidence and quickly determine the cause of malfunctioning hardware.
Abstract: This extensively revised edition of the bestselling Artech House book, RF Power Amplifiers for Wireless Communications, offers you a comprehensive, practical, and up-to-date understanding of how to tackle a power amplifier design with confidence and quickly determine the cause of malfunctioning hardware. Among the numerous updates, the Second Edition includes five new chapters on class AB PAs at GHz frequencies; switching PA modes at GHz frequencies; signals, modulation systems, and PA nonlinearities; power amplifier bias circuit design; and load-pull techniques. Chapters on efficiency enhancement methods and Class F design have been substantially extended, and many more practical examples and design tools are included on the accompanying CD-ROM. Supported with nearly 200 illustrations, the book contains the most complete survey of RF PA efficiency enhancement and linearization techniques in a single volume. It helps you design suitable matching networks which provide correct fundamental harmonic terminations for conventional (AB, B) high efficiency PA modes, understand the Class D, E, and F modes and their feasibility at microwave frequencies, and use envelope simulation techniques to analyze the effects of distortion in overdriven PAs. You learn how to maintain high efficiency operation at low points in an amplitude modulated signal envelope, including detailed coverage of the Doherty, Chireix, and Kahn techniques. Moreover, this authoritative resource helps you understand the possibilities and limitations of linearization methods, and offers guidance in objectively analyzing PA stability and oscillation problems.
532 citations
IBM1
TL;DR: A 0.13-mum SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented.
Abstract: A 0.13-mum SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P1dB of 10 to 12dBm, Psat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated
445 citations
TL;DR: In this paper, a software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters.
Abstract: A software-defined radio receiver is designed from a low-power ADC perspective, exploiting programmability of windowed integration sampler and clock-programmable discrete-time analog filters. To cover the major frequency bands in use today, a wideband RF front-end, including the low-noise amplifier (LNA) and a wide tuning-range synthesizer, spanning over 800 MHz to 6 GHz is designed. The wideband LNA provides 18-20 dB of maximum gain and 3-3.5 dB of noise figure over 800 MHz to 6 GHz. A low 1/f noise and high-linearity mixer is designed which utilizes the passive mixer core properties and provides around +70 dBm IIP2 over the bandwidth of operation. The entire receiver circuits are implemented in 90-nm CMOS technology. Programmability of the receiver is tested for GSM and 802.11g standards
433 citations
04 Dec 2006
TL;DR: In this paper, a new representation of the Volterra series is proposed, which is derived from a previously introduced modified VOLTERRA series, but adapted to the discrete time domain and reformulated in a novel way.
Abstract: A new representation of the Volterra series is proposed, which is derived from a previously introduced modified Volterra series, but adapted to the discrete time domain and reformulated in a novel way. Based on this representation, an efficient model-pruning approach, called dynamic deviation reduction, is introduced to simplify the structure of Volterra-series-based RF power amplifier behavioral models aimed at significantly reducing the complexity of the model, but without incurring loss of model fidelity. Both static nonlinearities and different orders of dynamic behavior can be separately identified and the proposed representation retains the important property of linearity with respect to series coefficients. This model can, therefore, be easily extracted directly from the measured time domain of input and output samples of an amplifier by employing simple linear system identification algorithms. A systematic mathematical derivation is presented, together with validation of the proposed method using both computer simulation and experiment
399 citations
TL;DR: The receiver and the on-chip antenna sections of a fully integrated 77-GHz four-element phased-array transceiver with on- chip antennas in silicon are presented.
Abstract: In this paper, we present the receiver and the on-chip antenna sections of a fully integrated 77-GHz four-element phased-array transceiver with on-chip antennas in silicon. The receiver section of the chip includes the complete down-conversion path comprising low-noise amplifier (LNA), frequency synthesizer, phase rotators, combining amplifiers, and on-chip dipole antennas. The signal combining is performed using a novel distributed active combining amplifier at an IF of 26 GHz. In the LO path, the output of the 52-GHz VCO is routed to different elements and can be phase shifted locally by the phase rotators. A silicon lens on the backside is used to reduce the loss due to the surface-wave power of the silicon substrate. Our measurements show a single-element LNA gain of 23 dB and a noise figure of 6.0dB. Each of the four receive paths has a gain of 37 dB and a noise figure of 8.0 dB. Each on-chip antenna has a gain of +2 dBi
383 citations
05 Jul 2006
TL;DR: It is demonstrated theoretically and by means of an experimental system that the high peak-to-average ratio in OFDM can be exploited constructively in visible light communication to intensity modulate LEDs.
Abstract: In this paper wireless communication using white, high brightness LEDs (light emitting diodes) is considered. In particular, the use of OFDM (orthogonal frequency division multiplexing) for intensity modulation is investigated. The high peak-to-average ratio (PAR) in OFDM is usually considered a disadvantage in radio frequency transmission systems due to non-linearities of the power amplifier. It is demonstrated theoretically and by means of an experimental system that the high PAR in OFDM can be exploited constructively in visible light communication to intensity modulate LEDs. It is shown that the theoretical and the experimental results match very closely, and that it is possible to cover a distance of up to one meter using a single LED.
353 citations
TL;DR: In this paper, a hybrid wideband EER power amplifier for the WLAN 802.11g system is proposed, which shows an overall efficiency of 36% and power-added efficiency of 28% for a WLAN IEEE 802.15.4 signal at 19dBm (80 mW) output power at 2.4 GHz.
Abstract: A comparison of envelope elimination and restoration (EER) and envelope tracking (ET) is discussed and a "hybrid" wideband EER power amplifier (PA) for the WLAN 802.11g system is proposed. A 60% efficiency (the output envelope signal power/input dc power) DC-20-MHz wideband envelope amplifier is designed for wideband EER and wideband ET (WBET) applications. A design method is developed to optimize the efficiency of the envelope amplifier for a given peak-to-average ratio and average slew rate of the envelope signal. An experimental "hybrid" Class-E EER system shows an overall efficiency (modulated RF output power/envelope amplifier dc input power) of 36% and power-added efficiency (the modulated RF output power/envelope amplifier dc input power plus RF input power) of 28% for a WLAN 802.11g signal at 19-dBm (80 mW) output power at 2.4 GHz. Digital predistortion, time alignment, and memory effect mitigation are implemented. The measured 3% error vector magnitude exceeds the 802.11g specification for 5% for a 54-Mb/s modulation signal
347 citations
TL;DR: In this paper, a high-efficiency wideband code-division multiple access (W-CDMA) base station amplifier is presented using high-performance GaN heterostructure field effect transistors to achieve high gain and efficiency with good linearity.
Abstract: A high-efficiency wideband code-division multiple-access (W-CDMA) base-station amplifier is presented using high-performance GaN heterostructure field-effect transistors to achieve high gain and efficiency with good linearity For high efficiency, class J/E operation was employed, which can attain up to 80% efficiency over a wide range of input powers and power supply voltages For nonconstant envelope input, the average efficiency is further increased by employing the envelope-tracking architecture using a wide-bandwidth high-efficiency envelope amplifier The linearity of overall system is enhanced by digital pre-distortion The measured average power-added efficiency of the amplifier is as high as 507% for a W-CDMA modulated signal with peak-to-average power ratio of 767 dB at an average output power of 372 W and gain of 100 dB We believe that this corresponds to the best efficiency performance among reported base-station power amplifiers for W-CDMA The measured error vector magnitude is as low as 174% with adjacent channel leakage ratio of -510 dBc at an offset frequency of 5 MHz
327 citations
TL;DR: It is shown that a critical design constraint for optimum bandwidth extension is the ratio of the drain capacitance of the driver transistor to the load capacitance, and recommends the use of different techniques for different capacitance ratios.
Abstract: Inductive-peaking-based bandwidth extension techniques for CMOS amplifiers in wireless and wireline applications are presented. To overcome the conventional limits on bandwidth extension ratios, these techniques augment inductive peaking using capacitive splitting and magnetic coupling. It is shown that a critical design constraint for optimum bandwidth extension is the ratio of the drain capacitance of the driver transistor to the load capacitance. This, in turn, recommends the use of different techniques for different capacitance ratios. Prototype wideband amplifiers in 0.18-mum CMOS are presented that achieve a measured bandwidth extension ratio up to 4.1 and simultaneously maintain high gain (>12 dB) in a single stage. Even higher enhancement ratios are shown through the introduction of a modified series-peaking technique combined with staggering techniques. Ultra-wideband low-noise amplifiers in 0.18-mum CMOS are presented that exhibit bandwidth extension ratios up to 4.9
319 citations
TL;DR: In this article, the first fully integrated 77-GHz phased-array transceiver is presented, which utilizes a local LO-path phase-shifting architecture to achieve beam steering and includes four transmit and receive elements, along with the LO frequency generation and distribution circuitry.
Abstract: Integration of mm-wave multiple-antenna systems on silicon-based processes enables complex, low-cost systems for high-frequency communication and sensing applications. In this paper, the transmitter and LO-path phase-shifting sections of the first fully integrated 77-GHz phased-array transceiver are presented. The SiGe transceiver utilizes a local LO-path phase-shifting architecture to achieve beam steering and includes four transmit and receive elements, along with the LO frequency generation and distribution circuitry. The local LO-path phase-shifting scheme enables a robust distribution network that scales well with increasing frequency and/or number of elements while providing high-resolution phase shifts. Each element of the heterodyne transmitter generates +12.5 dBm of output power at 77 GHz with a bandwidth of 2.5 GHz leading to a 4-element effective isotropic radiated power (EIRP) of 24.5 dBm. Each on-chip PA has a maximum saturated power of +17.5 dBm at 77 GHz. The phased-array performance is measured using an internal test option and achieves 12-dB peak-to-null ratio with two transmit and receive elements active
TL;DR: In this article, an ultra low power 2.4 GHz transceiver targeting wireless sensor network applications is presented, where the receiver front-end is fully passive, utilizing an integrated resonant matching network to achieve voltage gain and interface directly to a passive mixer.
Abstract: An ultra low power 2.4-GHz transceiver targeting wireless sensor network applications is presented. The receiver front-end is fully passive, utilizing an integrated resonant matching network to achieve voltage gain and interface directly to a passive mixer. The receiver achieves a 7-dB noise figure and -7.5-dBm IIP3 while consuming 330 muW from a 400-mV supply. The binary FSK transmitter delivers 300 muW to a balanced 50-Omega load with 30% overall efficiency and 45% power amplifier (PA) efficiency. Performance of the receiver topology is analyzed and simple expressions for the gain and noise figure of both the passive mixer and matching network are derived. An analysis of passive mixer input impedance reveals the potential to reject interferers at the mixer input with characteristics similar to an extremely high-Q parallel LC filter centered at the switching frequency
TL;DR: In this article, the Doherty amplifier is implemented using laterally diffused metal oxide semiconductor (LDMOS) transistors and measured using a WCDMA 4FA signal.
Abstract: In this article, we show that the Doherty amplifier is capable of delivering the stringent requirements of the base station power amplifiers. We explain the operation principles, including both linearity and efficiency improvements, and the basic circuit configuration of the amplifier. Advanced design methods to operate across wide bandwidth and improve the linearity are also described. For verification, the Doherty amplifier is implemented using laterally diffused metal oxide semiconductor (LDMOS) transistors and measured using a WCDMA 4FA signal. These results show that the Doherty amplifier is a promising candidate for base station power amplifiers with wide bandwidth, high efficiency, and linearity
TL;DR: This paper presents a multi-band multi-mode class-AB power amplifier, which utilizes continuously tunable input and output matching networks integrated in a low-loss silicon-on-glass technology to achieve the desired source and load impedance tunability.
Abstract: This paper presents a multi-band multi-mode class-AB power amplifier, which utilizes continuously tunable input and output matching networks integrated in a low-loss silicon-on-glass technology. The tunable matching networks make use of very high Q varactor diodes (Q>100 @ 2 GHz) in a low distortion anti-series configuration to achieve the desired source and load impedance tunability. A QUBIC4G (SiGe, ft=50 GHz) high voltage breakdown transistor (VCBO=14 V, VCEO>3.6 V) is used as active device. The realized adaptive amplifier provides 13 dB gain, 27-28 dBm output power at the 900, 1800, 1900 and 2100 MHz bands. For the communication bands above 1 GHz optimum load adaptation is facilitated resulting in efficiencies between 30%-55% over a 10 dB output power control range. The total chip area (including matching networks) of the amplifier is 8 mm2
TL;DR: In this article, a record optical fiber gain of 70 dB was obtained in a continuous-wave pumped fiber-optical parametric amplifier, where the spectral density of ASE was up to 180 mW/nm.
Abstract: A record optical fiber gain of 70 dB was obtained in a continuous-wave pumped fiber-optical parametric amplifier. Limitations due to saturation effects from amplified spontaneous emission (ASE) and due to stimulated Brillouin scattering in this unidirectional amplifier are discussed. The spectral density of ASE was up to 180 mW/nm in agreement with theoretical expectations, illustrating the possible use as a high brightness optical noise source
26 Jun 2006
TL;DR: In this paper, a CDTA-based quadrature oscillator circuit is proposed, which employs two current-mode allpass sections in a loop, and provides high-frequency sinusoidal oscillations in quadratures at high impedance output terminals of the CDTAs.
Abstract: A CDTA-based quadrature oscillator circuit is proposed. The circuit employs two current-mode allpass sections in a loop, and provides high-frequency sinusoidal oscillations in quadrature at high impedance output terminals of the CDTAs. The circuit has no floating capacitors, which is advantageous from the integrated circuit manufacturing point of view. Moreover, the oscillation frequency of this configuration can be made adjustable by using voltage controlled elements (MOSFETs), since the resistors in the circuit are either grounded or virtually grounded.
TL;DR: In this paper, the authors presented analytic and experimental comparisons for high-efficiency class-F and inverse-class-F amplifiers, where the analytic formula of the efficiencies, output powers, dc power dissipations and fundamental load impedances of both amplifiers were derived from the ideal current and voltage waveforms.
Abstract: This paper presents analytic and experimental comparisons for high-efficiency class-F and inverse class-F amplifiers. The analytic formula of the efficiencies, output powers, dc power dissipations, and fundamental load impedances of both amplifiers are derived from the ideal current and voltage waveforms. Based on the formula, the performances are compared with a reasonable condition: fundamental output power levels of class-F and inverse class-F amplifiers are conditioned to be identical. The results show that the inverse class-F amplifier has better efficiency than that of class-F amplifiers as the on-resistance of the transistor increases. For experimental comparison, we have designed and implemented the class-F and inverse class-F amplifiers at I-GHz band using a GaAs MESFET and analyzed the measured performances. Experimental results shows 10% higher power-added efficiency of the inverse class-F amplifier than that of the class-F amplifier, which verifies the waveform analysis.
TL;DR: In this paper, an error-free and pattern-independent wavelength conversion at 160 Gb/s was demonstrated using an optical bandpass filter (OBF) placed at the amplifier output.
Abstract: Error-free and pattern-independent wavelength conversion at 160 Gb/s is demonstrated. The wavelength converter utilizes a semiconductor optical amplifier (SOA) with a recovery time greater than 90 ps and an optical bandpass filter (OBF) placed at the amplifier output. This paper shows that an OBF with a central wavelength that is blue shifted compared to the central wavelength of the converted signal shortens the recovery time of the wavelength converter to 3 ps. The wavelength converter is constructed by using commercially available fiber-pigtailed components. It has a simple configuration and allows photonic integration.
Patent•
10 Mar 2006TL;DR: In this article, a beamforming radio frequency (RF) circuit includes a plurality of antennas, an adjust module, and a multiplicity of amplifiers, and the adjust module is operably coupled to interrelate coordinates of a signal with the plurality of adjusted signal components.
Abstract: A beamforming radio frequency (RF) circuit includes a plurality of antennas, a plurality of amplifiers and an adjust module. The plurality of antennas is operably coupled to interrelate a plurality of beamformed signal components with a beamformed signal. The plurality of amplifiers is operably coupled to interrelate the plurality of beamformed signal components with a plurality of adjusted signal components. The adjust module is operably coupled to interrelate coordinates of a signal with the plurality of adjusted signal components.
Patent•
07 Apr 2006
TL;DR: In this article, a device and method for providing power line communications via an underground residential distribution power system is provided, which includes a medium voltage interface device that may include a first port configured to communicate over the power line and a network interface.
Abstract: A device and method for providing power line communications via an underground residential distribution power system is provided. One embodiment of the present invention includes a medium voltage interface device that may include a first port configured to communicate over the power line and a network interface. A first amplifier may form part of a first communication path between the first port and the network interface and be configured to amplify data signals transmitted via the first port. In addition, a second amplifier may form part of a second communication path between the first port and the network interface and be configured to amplify data signals received via the first port. In addition, the embodiment may include a diplexer forming part of the first communication path between the first amplifier and the first port and forming part of the second communication path between the second amplifier and the first port. The device may include an electro-optic converter coupled to the network interface to convert between electrical and optic data signals, wherein the network interface is configured to communicate via one or more fiber optic conductors.
TL;DR: In this paper, the authors proposed a current mode Kerwin-Huelsman-Newcomb (KHN) filter employing only two current differencing transconductance amplifiers (CDTA) and two grounded capacitors.
Abstract: This study proposes a current mode (CM) Kerwin–Huelsman–Newcomb (KHN) filter employing only two current differencing transconductance amplifiers (CDTA) and two grounded capacitors. It is concluded that the circuit described here offers a simpler and more economical alternative to other CM KHN filters reported previously in literature.
Patent•
14 Dec 2006TL;DR: In this paper, a method and apparatus for controlling a selectable voltage audio power output stage provides a mechanism for raising the selected power amplifier output voltage in time for the arrival of signal peaks to avoid clipping.
Abstract: A method and apparatus for controlling a selectable voltage audio power output stage provides a mechanism for raising the selected power amplifier output voltage in time for the arrival of signal peaks to avoid clipping. Signal peaks may either be delayed by delaying an increase in volume control level or enabling signal compression for a predetermined time period, so that sufficient time is provided for the amplifier power supply to stabilize at a higher operating voltage when an increase of power supply voltage is selected. Alternatively, a signal level may be determined at an upstream source, such as a decoder or filter that provides information in sufficient advance of the arrival of the peaks, and used to control the power supply selection, so that the higher power supply voltage level is selected in advance of arrival of the signal peaks that would otherwise cause clipping at the power amplifier output.
TL;DR: A scalable architecture for a high-power, high-brightness, solid-state laser based on coherent combinations of master oscillator power amplifier chains and Adaptive optics correct the wavefront of each amplified beamlet.
Abstract: We demonstrate a scalable architecture for a high-power, high-brightness, solid-state laser based on coherent combinations of master oscillator power amplifier chains. A common master oscillator injects a sequence of multikilowatt Nd:YAG zigzag slab amplifiers. Adaptive optics correct the wavefront of each amplified beamlet. The beamlets are tiled side by side and actively phase locked to form a single output beam. The laser produces 19 kW with beam quality <2x diffraction limited. To the best of our knowledge, this is the brightest cw solid-state laser demonstrated to date.
24 Apr 2006
TL;DR: This paper focuses on cascode-based topologies, analyzing the loss mechanisms and giving direction to optimize the design, and identifies a new dissipative mechanism, peculiar of the cascode implementation, and proposes a circuit solution to minimize its effect.
Abstract: Power efficiency in switched common source class-E amplifiers is usually obtained at the expense of device stress. Device stacking is a viable way to reduce voltage drops across a single device, improving long-term reliability. In this paper, we focus on cascode-based topologies, analyzing the loss mechanisms and giving direction to optimize the design. In particular, a new dissipative mechanism, peculiar of the cascode implementation, is identified and a circuit solution to minimize its effect is proposed. Prototypes, realized in a 0.13-/spl mu/m CMOS technology demonstrate 67% PAE while delivering 23 dBm peak power at 1.7 GHz. Good bandwidth was also realized with greater than 60% PAE over the frequency range of 1.4-2 GHz.
TL;DR: An optical parametric chirped-pulse amplifier producing infrared 20 fs (3-optical-cycle) pulses with a stable carrier-envelope phase with well-suppressed background of parametric superfluorescence is demonstrated.
Abstract: We demonstrate an optical parametric chirped-pulse amplifier producing infrared 20 fs (3-optical-cycle) pulses with a stable carrier-envelope phase. The amplifier is seeded with self-phase-stabilized pulses obtained by optical rectification of the output of an ultrabroadband Ti:sapphire oscillator. Energies of -80 microJ with a well-suppressed background of parametric superfluorescence and up to 400 microJ with a superfluorescence background are obtained from a two-stage parametric amplifier based on periodically poled LiNbO3 and LiTaO3 crystals. The parametric amplifier is pumped by an optically synchronized 1 kHz, 30 ps, 1053 nm Nd:YLF amplifier seeded by the same Ti:sapphire oscillator.
TL;DR: In this paper, a four-element fiber array has demonstrated 470 watts of coherently phased, linearly polarized light energy in a single far-field spot, each element consists of a single-mode fiber-amplifier chain.
Abstract: A four-element fiber array has demonstrated 470 watts of coherently phased, linearly polarized light energy in a single far-field spot. Each element consists of a single-mode fiber-amplifier chain. Phase control of each element is achieved with a Lithium-Niobate phase modulator.
A master laser provides a linearly polarized, narrow linewidth signal that is split into five channels. Four channels are individually amplified using polarization maintaining fiber power amplifiers. The fifth channel is used as a reference arm. It is frequency shifted and then combined interferometrically with a portion of each channel's signal. Detectors sense the heterodyne modulation signal, and an electronics circuit measures the relative phase for each channel. Compensating adjustments are then made to each channel's phase modulator.
This effort represents the results of a multi-year effort to achieve high power from a single element fiber amplifier and to understand the important issues involved in coherently combining many individual elements to obtain sufficient optical power for directed energy weapons. Northrop Grumman Corporation and the High Energy Laser Joint Technology Office jointly sponsored this work.
TL;DR: A gain control mechanism is introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets.
Abstract: An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-mum 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7plusmn0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets
TL;DR: In this paper, the authors measured phase noise in thin-film superconducting coplanar waveguide resonators and found that the ratio between the noise power in the phase and amplitude directions is large, in excess of 30 dB.
Abstract: We have measured noise in thin-film superconducting coplanar waveguide resonators. This noise appears entirely as phase noise, equivalent to a jitter of the resonance frequency. In contrast, amplitude fluctuations are not observed at the sensitivity of our measurement. The ratio between the noise power in the phase and amplitude directions is large, in excess of 30 dB. These results have important implications for resonant readouts of various devices such as detectors, amplifiers, and qubits. We suggest that the phase noise is due to two-level systems in dielectric materials.
TL;DR: This work proposes a compensation technique that places the regulator's amplifier in a local replica feedback loop, stabilizing the regulator by increasing the amplifier bandwidth while lowering its gain, and shows that for reasonable mismatch between the replica and actual loads, regulator performance is uncompromised.
Abstract: Supply-regulated phase-locked loops rely upon the VCO voltage regulator to maintain a low sensitivity to supply noise and hence low overall jitter. By analyzing regulator supply rejection, we show that in order to simultaneously meet the bandwidth and low dropout requirements, previous regulator implementations used in supply-regulated PLLs suffer from unfavorable tradeoffs between power supply rejection and power consumption. We therefore propose a compensation technique that places the regulator's amplifier in a local replica feedback loop, stabilizing the regulator by increasing the amplifier bandwidth while lowering its gain. Even though the forward gain of the amplifier is reduced, supply noise affects the replica output in addition to the actual output, and therefore the amplifier's gain to reject supply noise is effectively restored. Analysis shows that for reasonable mismatch between the replica and actual loads, regulator performance is uncompromised, and experimental results from a 90 nm SOI test chip confirm that with the same power consumption, the proposed regulator achieves at least 4 dB higher supply rejection than the previous regulator design. Furthermore, simulations show that if not for other supply rejection-limiting components in the PLL, the supply rejection improvement of the proposed regulator is greater than 15 dB.
Patent•
27 Oct 2006
TL;DR: In this paper, an iterative method for configuring the lamp circuit includes determining the load trajectory of each amplifier under all operating conditions, and overlaying it on a polar-plot showing regions of stability, conditional stability, and instability.
Abstract: A plasma lamp with a positive-loop feedback topology, having a resonating waveguide body and at least one amplifier critically coupled to the body which is stable under all operating conditions both before a plasma is formed and after the plasma reaches steady state. An iterative method for configuring the lamp circuit includes determining the load trajectory of each amplifier under all operating conditions, and overlaying it on a polar-plot showing regions of stability, conditional stability, and instability. If the load trajectory passes through an unstable region, circuit alterations are made to avoid that region.